Memory Interface Clock Division Across Multiple Non-Volatile Memories
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Solution Overview
Problem
The increasing data throughput in computing systems often exceeds the data bandwidth or communication speed of interfaces connected to non-volatile memory devices, leading to data bottlenecks and degraded performance, particularly in solid-state drives (SSDs) based on flash memories.
Innovation Solution
A memory system with an interface circuit that divides a received clock signal into multiple clock signals to accommodate a plurality of non-volatile memories, allowing for adaptive operating frequency adjustment and synchronized data exchange, thereby enhancing data throughput and system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data throughput is increased to meet computing system demands, then data bandwidth requirement increases, but interface communication speed becomes insufficient causing data bottlenecks
Solution Approach 1:
The interface circuit is divided into multiple parallel interfaces (first interface circuit, second interface circuit, etc.), each handling a portion of the data throughput. This segmentation allows the system to scale data bandwidth by activating additional interface circuits rather than relying on a single high-speed interface, thus resolving the bottleneck without requiring a proportional increase in individual interface speed.
Solution Approach 2:
Multiple interface circuits are combined to work in parallel, aggregating their individual data bandwidths to achieve higher overall throughput. The memory controller coordinates these multiple interfaces to handle data transactions simultaneously, effectively merging their capabilities to meet the increased data throughput demands of computing systems.
2Quantity of substance
If multiple non-volatile memories are connected to increase capacity, then data storage capacity increases, but clock synchronization complexity increases
Solution Approach 1:
The clock signal distribution is segmented into hierarchical levels: a first clock from the memory controller, divided into second clocks by first interface circuits, and further divided into third clocks by second interface circuits. This segmentation allows each memory device to operate at appropriate clock frequencies while maintaining synchronization through the structured division scheme.
Solution Approach 2:
Interface circuits act as intermediary devices between the memory controller and multiple non-volatile memories. These intermediaries receive the master clock signal, perform necessary frequency division, and distribute synchronized clocks to connected memory devices, thereby simplifying the overall synchronization complexity by centralizing clock management at the interface level.
3Productivity
If operating frequency is increased to improve data processing speed, then data throughput improves, but system stability decreases
Solution Approach 1:
The system employs dynamic clock frequency adjustment where different interface circuits and memory devices operate at different clock frequencies based on their specific requirements. The memory controller can adaptively manage clock distributions, allowing high-speed operation where needed while maintaining stable operation elsewhere, thus achieving high data processing speed without compromising overall system stability.
Solution Approach 2:
Different portions of the memory system operate at different clock frequencies optimized for their specific functions. Critical high-speed paths use higher frequencies while other portions maintain lower, more stable frequencies. This local optimization allows the system to achieve high data processing speed in essential pathways without requiring the entire system to operate at high frequencies, thereby maintaining stability.
Data Source
AI summary
A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.