Clock Signal Division Switching for Fast PLL Startup Stability
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Solution Overview
Problem
Fluctuations in the frequency of clock signals during the initialization of electronic circuits can cause errors, leading to inefficiencies as existing solutions require waiting for stabilization, resulting in standby time waste.
Innovation Solution
A dual-frequency division mechanism using a phase-locked loop and frequency dividers, controlled by a stability signal, to generate an output clock signal that stabilizes quickly, ensuring stable operation without delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal frequency is allowed to fluctuate during initialization, then the standby time is reduced and productivity is improved, but the reliability deteriorates due to frequency-related errors
Solution Approach 1:
The patent divides the clock signal generation into two separate paths: a first frequency division path that operates during initialization when the PLL is stabilizing, and a second frequency division path that operates after stabilization. This segmentation allows the system to use appropriate division factors for each phase, reducing standby time while maintaining reliability during normal operation.
Solution Approach 2:
The patent dynamically switches between different frequency division factors based on the stabilization state of the PLL. A control signal transitions from a first value to a second value, changing the division factor from a first value to a second value. This dynamic adaptation allows the system to optimize performance during initialization while ensuring stability during normal operation.
2Reliability
If a higher frequency division factor is used during initialization, then frequency-related errors are minimized, but the output clock signal frequency is reduced and productivity decreases
Solution Approach 1:
The patent uses a dynamic switching mechanism that changes the frequency division factor based on the PLL stabilization state. During initialization, a first frequency division factor is used to minimize frequency errors. After stabilization, a second frequency division factor (which may be smaller or equal to the first) is used to maximize output frequency while maintaining stability. This dynamic approach resolves the contradiction between error reduction and productivity.
Solution Approach 2:
The patent changes the division factor parameter based on the operational phase. The control signal transitions from a first value to a second value, which corresponds to changing the division factor from a first value to a second value. This parameter change allows the system to optimize for reliability during initialization and for productivity during normal operation.
Data Source
AI summary
An electronic device includes a first electronic circuit that generates a first clock signal and a second signal indicating a state of stability of a frequency of the first clock signal. The second signal has a first value during a first period and a second value after the first period. A second electronic circuit of the electronic device generates an output clock signal having a frequency equal to the frequency of the first clock signal divided by a first factor when the second signal is at the first value. Alternatively, the second electronic circuit generates the output clock signal having the frequency of the first clock signal, or a frequency equal to the frequency of the first clock signal divided by a second factor smaller than the first factor, when the second signal changes to the second value.