Clock Division Timing Alignment for Stable Internal Clock Generation
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Solution Overview
Problem
As the operating speed of computer systems increases, the frequency of system clock signals also rises, leading to challenges in generating stable internal clock signals with lower frequencies for semiconductor apparatuses, which are crucial for reliable data communication and synchronization.
Innovation Solution
A clock generating circuit comprising a first division circuit, a buffer circuit, a delay circuit, and a second division circuit, along with an enable control circuit, is used to generate synchronized internal clock signals by adjusting the operation timing of these circuits based on specific internal clock signals, ensuring that the generated internal clock signals have consistent characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of system clock signal is increased to improve operating speed, then productivity increases, but generating stable internal clock signals becomes more difficult
Solution Approach 1:
The patent divides the clock signal generation into multiple stages using first and second division circuits. The first division circuit divides the high-frequency system clock signal into intermediate frequency signals, and the second division circuit further divides these into lower frequency internal clock signals. This segmentation allows stable internal clock generation from high-frequency system clocks by breaking down the frequency transformation into manageable steps.
Solution Approach 2:
The patent introduces a delay locked loop circuit as an intermediary between the division circuits and the final clock output. This intermediary component adjusts and stabilizes the phase and frequency of clock signals, ensuring that internal clock signals remain stable even when the system clock frequency varies. The delay locked loop acts as a buffer that isolates the stability requirements from the high-frequency system clock.
2Productivity
If clock division circuit generates internal clock signal from high frequency system clock, then productivity increases, but synchronization accuracy may deteriorate
Solution Approach 1:
The patent employs a delay locked loop circuit that uses feedback mechanisms to maintain synchronization accuracy. The circuit continuously monitors the phase relationship between system clock signals and internal clock signals, and adjusts the delay accordingly to maintain precise synchronization. This feedback ensures that even when dividing high-frequency clocks, the internal clocks remain accurately synchronized with the system clock edges.
Solution Approach 2:
The patent uses preliminary division in the first division circuit to create intermediate frequency signals before the second division. This preliminary action reduces the frequency ratio that needs to be handled in subsequent stages, making it easier to maintain synchronization accuracy. By breaking down the frequency division into preliminary steps, the circuit maintains better phase alignment and timing relationships.
3Reliability
If multiple division circuits are used to generate internal clock signals, then reliability improves, but device complexity increases
Solution Approach 1:
The patent combines the delay adjustment functionality and clock division functionality into an integrated circuit structure where the delay locked loop circuit works in conjunction with the division circuits. By merging these functions and using shared control signals and common clock paths, the patent reduces the overall complexity that would otherwise result from completely separate circuits. The enable control circuit also merges control functions to coordinate the operation of multiple division circuits efficiently.
Data Source
AI summary
A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. Operation timing of the second division circuit is adjusted based on one of the first group of internal clock signals generated by the first division circuit.