Clock Domain Crossing Buffer Synchronization for Ordered Data Transfer
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Solution Overview
Problem
Conventional clock domain crossing circuits fail to properly order data transfer requests between different clock domains, leading to issues such as data incoherency and loss due to metastability and improper synchronization.
Innovation Solution
A method and circuit that generate synchronized current buffer signals in both source and destination clock domains to ensure the correct buffer is used for data transfer, delaying transfers when the buffers do not match, thereby maintaining data coherency and preventing loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synchronization circuitry is used to synchronize data transfer requests between clock domains, then data transfer requests can be synchronized, but the proper ordering of data transfer requests is not maintained in the destination clock domain
Solution Approach 1:
The patent applies preliminary action by generating and asserting the current buffer indicator signal in the destination clock domain before synchronizing it to the source clock domain. This ensures that the source clock domain has advance knowledge of which buffer is currently active in the destination domain, allowing it to properly order data transfer requests before they are processed, thus preventing ordering issues at the destination.
2Productivity
If double buffers are used in the source clock domain to increase interface bandwidth, then data transfer capacity is improved, but data incoherency and data loss occur due to improper buffer selection
Solution Approach 1:
The patent implements feedback by continuously monitoring the current buffer status in the destination clock domain and communicating this information back to the source clock domain through synchronized buffer indicator signals. This feedback mechanism ensures that the source clock domain always knows which buffer is currently active in the destination domain, enabling it to direct data transfers to the correct buffer and maintain data coherency while utilizing double buffering for increased bandwidth.
3Reliability
If data transfer requests are synchronized from source to destination clock domain, then synchronization is achieved, but metastability issues arise leading to data loss
Solution Approach 1:
The patent uses the buffer indicator signal as an intermediary that resolves the metastability problem. Instead of directly synchronizing data transfer requests from source to destination clock domains (which causes metastability), the buffer indicator signal is generated in the destination domain, synchronized to the source domain, and used to control buffer selection. This intermediary approach eliminates direct metastability-prone signal transitions while maintaining proper synchronization.
Data Source
AI summary
Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination domain current buffer signal indicates a first or second data buffer in a source clock domain as a current buffer for use during a current data transfer cycle. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicating the current buffer generated. A source data transfer request signal is generated based on the source domain current buffer signal and the source data transfer request signal synchronized to generate a destination domain data transfer request signal. Transfer of data between a memory in the destination clock domain is delayed to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.