Clock Domain Data Transfer Using Validated Codewords

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Solution Overview

Problem

Data correctness is not guaranteed when transferring information between different clock domains due to metastability issues, which can lead to data coherency loss and functional errors.

Innovation Solution

An electronic circuit with an encoding circuit in the source clock domain that encodes data into codewords and a reception circuit in the destination clock domain to decode and discard invalid codewords, ensuring data integrity by filtering out incorrect values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transferred directly between different clock domains, then transfer speed is improved, but data correctness deteriorates due to metastability

Engineering Contradiction:
Improvedata transfer speedVSAvoiddata correctness
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The encoding circuit performs encoding on data before it is transferred across the clock domain boundary. This preliminary encoding ensures that even if metastability occurs during transfer, the encoded structure allows the receiving circuit to identify and discard invalid codewords, thereby maintaining data correctness while enabling direct fast transfer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The encoding circuit and decoding circuit act as intermediaries that protect the data transfer process. The encoding circuit transforms data into codewords with specific properties, and the decoding circuit reconstructs or discards data based on validation, thereby mediating between the source and destination clock domains to ensure correctness without sacrificing transfer speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If encoding and decoding circuits are added to ensure data correctness, then data reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata correctnessVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The encoding circuit changes the parameters of the data by transforming it into codewords with specific structural properties. This parameter transformation enables the receiving circuit to easily validate and detect errors, achieving high reliability with relatively simple validation logic that checks codeword properties rather than complex error analysis.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If validation and discarding of invalid codewords is implemented, then data purity is improved, but processing time increases

Engineering Contradiction:
Improvedata purityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The decoding circuit performs only the necessary validation actions to identify invalid codewords based on their encoded structure, rather than fully processing and analyzing each codeword's content. This partial validation approach ensures data purity by discarding invalid codewords while minimizing the time spent on verification, as the encoding structure enables quick validation decisions.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10090965B2Electronic circuit and method for transferring data between clock domains
Publication Date: 2018.10.02 INFINEON TECHNOLOGIES AG
  • US10090965B2 patent drawing
  • US10090965B2 patent drawing
  • US10090965B2 patent drawing

AI summary

According to one embodiment, an electronic circuit is described comprising a first clock domain configured to operate according to a first clock signal, a second clock domain configured to operate according to a second clock signal different from the first clock signal, an encoding circuit, in the first clock domain, configured to encode data to be transmitted from the first clock domain to the second clock domain into codewords and configured to supply the codewords to an interface between the first clock domain and the second clock domain and a reception circuit, in the second clock domain, configured to receive data words from the interface, to decode valid codewords and to discard invalid codewords.