Clock Domain Crossing Verification with Constraint Setup Assistance
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Solution Overview
Problem
Design verification tools for clock domain crossings in electronic systems produce a large volume of results, making manual resolution of violations time-consuming and error-prone, often due to design errors or setup issues.
Innovation Solution
A design verification tool performs static checks on circuit designs, identifies violations, and generates additional design constraints iteratively using heuristics to address clock domain crossing issues, reducing future violations by analyzing and grouping clock signals, synchronization circuitry, and input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If design verification tools perform comprehensive static checks on clock domain crossings, then detection precision of violations is improved, but the volume of results increases making manual analysis more time-consuming and error-prone
Solution Approach 1:
The patent segments the large volume of clock domain crossing violations into groups based on shared characteristics such as source register, destination register, and clock domain. This segmentation allows verification engineers to analyze grouped violations rather than individual ones, significantly reducing manual analysis time while maintaining detection precision through the use of design constraint sets that characterize each group's violation patterns
Solution Approach 2:
The patent introduces design constraint sets as an intermediary between the verification tool and the engineer. These constraint sets automatically characterize groups of violations and provide setup assistance, acting as a mediator that translates raw violation data into actionable insights. This intermediary layer reduces the cognitive load on engineers and minimizes manual analysis time while preserving detection accuracy
2Reliability
If verification engineers manually analyze each clock domain crossing violation, then accuracy of identifying design errors is improved, but productivity decreases due to the large volume of results
Solution Approach 1:
The patent performs preliminary actions by automatically generating design constraint sets that characterize groups of violations before engineer analysis. These pre-prepared constraint sets include information about source/destination registers, clock domains, and violation patterns, allowing engineers to quickly assess accuracy without manually examining each violation. This preliminary organization maintains reliability while dramatically improving productivity
Solution Approach 2:
The patent implements feedback mechanisms where the verification tool provides structured information about violation groups and their characteristics. This feedback loop allows engineers to efficiently verify accuracy by reviewing summarized data rather than raw violations, and to quickly identify whether violations stem from design errors or setup issues, thereby improving both reliability and productivity
3Reliability
If the verification tool generates detailed analysis reports for all clock domain crossing violations, then completeness of verification is improved, but device complexity for processing and analyzing results increases
Solution Approach 1:
The patent merges multiple individual violation analyses into consolidated design constraint sets that represent groups of violations with shared characteristics. By combining information about source registers, destination registers, clock domains, and violation patterns into unified constraint sets, the tool maintains complete verification coverage while reducing processing complexity. Engineers work with merged constraint sets rather than individual violation reports, simplifying the analysis process
Data Source
AI summary
A computing system can perform static verification operations on a circuit design with a first set of design constraints characterizing portions of an electronic device described by the circuit design and identify one or more violations associated with clock domain crossings in the circuit design. The computing system can analyze the circuit design and the first set of the design constraints to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the first set of the design constraints, and generate one or more additional design constraints to integrate into the first set of the design constraints based on the analysis of the circuit design and the first set of the design constraints. The computing system can re-perform the static verification operations on the circuit design based on a second set of the design constraints that includes the additional design constraints.