Clock Domain Crossing Circuit Using Asynchronous FIFO and Gray Code
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Solution Overview
Problem
Existing digital circuit designs face challenges in efficiently transferring signals across different clock and power domains without requiring coordinated power-up or power-down sequences, clock synchronization, or additional system assumptions, especially when one domain is inactive or resetting independently.
Innovation Solution
The implementation of a domain-crossing circuit with transmit-side and receive-side circuitry using asynchronous First-In First-Out (FIFO) buffers and non-volatile elements like Flip-Flops coupled with latch isolators to retain and transfer read and write pointer values across domains, allowing independent management of power and clock states without clock signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock-domain crossing techniques are used, then data transfer between clock domains is enabled, but coordinated reset sequences and clock synchronization are required, increasing system complexity
Solution Approach 1:
The circuit is divided into independent transmit-side and receive-side domains with no shared clock signals. Each domain operates autonomously with its own clock, eliminating the need for clock synchronization and coordinated reset sequences between domains.
Solution Approach 2:
An asynchronous FIFO buffer is introduced as an intermediary data structure between the transmit and receive domains. The FIFO uses gray-coded pointers (read pointer and write pointer) that can be safely transferred between clock domains without synchronization, enabling reliable data transfer while maintaining domain independence.
2Use of energy by moving object
If power domains are partitioned for independent power management, then power efficiency is improved, but data transfer between power domains becomes challenging when one domain is inactive
Solution Approach 1:
The transmit side prepares data and increments the write pointer in advance, storing data in the FIFO buffer before the receive side is ready. This allows the transmit domain to operate independently without waiting for the receive domain's readiness, enabling power-efficient independent domain operation.
Solution Approach 2:
The receive pointer value is transferred from the receive domain to the transmit domain, providing feedback about the FIFO buffer's readout position. This feedback mechanism enables the transmit side to verify buffer status and continue operation independently, even when the receive domain is powered down or resetting.
3Stability of the object's composition
If clock signals are transferred between domains, then synchronized operation is achieved, but clock synchronization requirements increase system complexity and reduce flexibility
Solution Approach 1:
Clock signal transfer between domains is completely removed from the system. Each domain maintains its own independent clock, and data transfer is achieved through the asynchronous FIFO mechanism using gray-coded pointers that do not require clock synchronization.
Solution Approach 2:
The pointer values are encoded in gray code instead of binary, allowing safe transfer between clock domains. The gray-coded representation ensures that only one bit changes between consecutive values, preventing metastability and enabling reliable asynchronous operation without clock synchronization.
4Adaptability or versatility
If one domain resets independently without coordination, then domain independence is improved, but data integrity during reset transitions becomes problematic
Solution Approach 1:
The FIFO buffer provides a cushioning mechanism that can absorb reset transitions in one domain without affecting the other. Data is buffered in the FIFO, and the gray-coded pointers ensure that reset transitions do not cause data corruption or loss, allowing independent reset operation while maintaining data integrity.
Data Source
AI summary
An electronic circuit includes transmit-side circuitry and receive-side circuitry. The transmit-side circuitry belongs to a first domain of the circuit and is configured to transmit a data signal from the first domain to a second domain of the circuit. The receive-side circuitry belongs to the second domain and is configured to receive the transmitted data signal. The receive-side circuitry is configured to transfer to the transmit-side circuitry a read pointer value indicative of a readout position in a buffer memory that buffers the data signal, and to retain the read pointer value in a non-volatile element that is accessible to the transmit-side circuitry.