Clock Domain Crossing Architecture for High Frequency Trading
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Solution Overview
Problem
In high-frequency trading environments, conventional techniques for synchronizing clock domains increase latency and fail to eliminate jitter-induced bit errors, while error detection methods also increase round-trip latency and may not comply with communication protocols.
Innovation Solution
The proposed solution involves an apparatus with functional circuitry that generates an output in a first clock domain, computes an error detection code, and formats the output based on a communication protocol in a second clock domain, while using a cleanup phase locked loop to filter jitter and synchronize the local clock with the recovered clock without passing jitter, and error detection circuitry to evaluate and cancel bit errors without increasing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock domain synchronization techniques are used, then clock domains are synchronized, but round-trip latency increases
Solution Approach 1:
A cleanup PLL circuit is introduced as an intermediary between the recovered clock and the local clock domains. The cleanup PLL filters jitter from the recovered clock while generating a clean reference clock, enabling synchronization without adding latency to the critical data path. The phase detector and variable delay line act as mediators to adjust phase differences without increasing round-trip latency.
Solution Approach 2:
The synchronization function is segmented into separate dedicated circuits: a cleanup PLL for jitter filtering, a phase detector for phase difference detection, and a variable delay line for phase adjustment. This segmentation allows each component to perform its function independently without blocking the main data path, thus maintaining low latency while achieving clock domain synchronization.
2Reliability
If error detection methods are implemented, then bit errors are detected, but round-trip latency increases
Solution Approach 1:
Error detection codes are computed in advance during the data processing stage in the first clock domain, before the data needs to be transmitted or further processed. The encoding circuitry computes error detection codes based on the output data, so that when data crosses clock domains, error detection has already been performed without adding latency to the critical path.
Solution Approach 2:
The error detection process is integrated into the continuous data flow between clock domains. The encoding circuitry operates continuously in parallel with the format circuitry, computing error detection codes without interrupting or pausing the data processing stream, thus maintaining continuous useful action without latency increases.
3Reliability
If jitter is passed from recovered clock to local clock, then clock synchronization is achieved, but bit errors increase
Solution Approach 1:
The cleanup PLL circuit converts the harmful jitter present in the recovered clock into a beneficial clean reference clock. By filtering out jitter through the PLL's natural low-pass filtering characteristic, the circuit transforms the noisy recovered clock signal into a stable, jitter-free reference clock that can safely synchronize the local clock domain without introducing bit errors.
Solution Approach 2:
The cleanup PLL acts as an intermediary that isolates the local clock domain from jitter in the recovered clock. The phase detector and variable delay line serve as additional intermediaries that detect and correct phase differences without transmitting jitter, thereby protecting the local clock domain from harmful jitter while maintaining synchronization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces round-trip latency and bit errors, ensuring compliant communication while maintaining low latency and preventing bit errors from being transmitted, thus enhancing the efficiency of high-frequency trading operations.
Implementation Method 1
a cleanup phase locked loop (PLL) circuit that filter jitter of the recovered clock
Implementation Method 2
a variable delay line that adjusts a phase of the reference clock based on an output of the phase detector
Data Source
AI summary
A fast clock domain crossing architecture for high frequency trading includes a receiver that recovers data and a clock of a first clock domain from a communication from an exchange, functional circuitry that generates and a buy/sell command based on the recovered data and the recovered clock, format circuitry that formats the command in a second clock domain, and a transmitter that transmits the formatted command to the exchange. The architecture further includes error detection circuitry that detects bit errors that arise from an asynchronous boundary of the clock domains without increasing a round-trip latency, and/or synchronization circuitry that synchronizes the clock domains, where the synchronization circuitry includes a cleanup PLL that filters input jitter and a phase detector and variable delay line that compensate for latency within the architecture.