Clock Domain Crossing Using Lookup Table Synchronization
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Solution Overview
Problem
Integrated circuits with multiple clock domains face challenges in maintaining data and control synchronization across different clock frequencies, leading to potential operational errors and inefficiencies when dynamically adjusting clock frequencies to reduce power consumption.
Innovation Solution
A method is implemented where a counter is initialized based on the clock frequency ratio between clock domains, allowing control and data to be synchronized by generating a signal when the counter reaches a predetermined value, ensuring that control information is read before paired data, thus maintaining the correct pipeline offset and reducing transition delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic clock frequency adjustments are made to reduce power consumption, then energy efficiency is improved, but data synchronization between clock domains becomes more difficult to maintain
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the relationship between clock cycle counts of different clock domains in a lookup table before data transfer occurs. When transferring data between clock domains with different frequencies, the system retrieves the pre-computed clock cycle relationship from the lookup table to determine when data is ready, eliminating the need for complex real-time frequency comparison logic and ensuring synchronization accuracy even when clock frequencies are dynamically adjusted.
2Measurement precision
If a counter is used to track clock events for synchronization, then data transfer timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the relationship between clock cycle counts of different clock domains in a lookup table before data transfer occurs. When transferring data between clock domains with different frequencies, the system retrieves the pre-computed clock cycle relationship from the lookup table to determine when data is ready, eliminating the need for complex real-time frequency comparison logic and ensuring synchronization accuracy even when clock frequencies are dynamically adjusted.
Solution Approach 2:
The patent introduces an intermediary mechanism by using a lookup table that mediates between the first clock domain and the second clock domain. Instead of directly comparing clock frequencies or using complex counters, the lookup table serves as an intermediary that provides pre-computed timing relationships, simplifying the synchronization logic while maintaining precise timing accuracy for data transfer.
3Reliability
If control information is stored in a separate control queue ahead of data, then operational correctness is improved, but transition delays increase
Solution Approach 1:
The patent applies preliminary action by storing control information in a control queue ahead of the actual data transfer, allowing the receiving circuit to prepare for incoming data by retrieving synchronization parameters from the lookup table in advance. This preliminary preparation ensures that when data arrives, the receiving circuit is ready to process it immediately, minimizing transition delays while maintaining operational correctness.
Data Source
AI summary
An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading.