Clock Domain Crossing Interface Using Phase-Adaptive Re-Timing
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Solution Overview
Problem
In electronic systems, multiple integrated circuits operating in different clock domains often face synchronization issues during clock domain crossing, leading to inefficiencies in signal traversal between these domains.
Innovation Solution
The implementation of transmitting and receiving circuitry that re-times digital input signals based on the phases of clocking signals in both the transmitting and receiving domains, using TED and TCD circuitry for the transmitting cluster and RED and RCD circuitry for the receiving cluster, to synchronize signals across clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If signals traverse between multiple integrated circuits operating in different clock domains, then data communication between circuits is enabled, but synchronization issues and errors occur during clock domain crossing
Solution Approach 1:
The patent introduces a clock domain crossing interface as an intermediary mechanism between circuits operating in different clock domains. This interface includes a writer circuit in the first clock domain and a reader circuit in the second clock domain, which act as mediators to safely transfer data across the clock domain boundary, preventing synchronization issues and errors that would occur with direct signal traversal.
Solution Approach 2:
The patent employs preliminary actions by using handshaking signals and control logic to prepare and coordinate data transfer before the actual data movement occurs. The writer circuit generates control signals that pre-synchronize the data transfer operation, ensuring that the reader circuit is ready to capture the data at the correct moment in the second clock domain, thereby preventing synchronization errors.
2Productivity
If traditional clock domain crossing methods are used, then signal traversal between clock domains is achieved, but data integrity and error rates are compromised
Solution Approach 1:
The patent implements feedback mechanisms through handshaking signals that flow back from the reader circuit to the writer circuit. These feedback signals confirm successful data capture and trigger the next data transfer operation. This closed-loop feedback system ensures data integrity by verifying each transfer operation and maintaining synchronization between the two clock domains, preventing errors while preserving traversal efficiency.
3Productivity
If multiple integrated circuits operate in their own clock domains independently, then each circuit can optimize its performance, but synchronization issues arise during signal traversal
Solution Approach 1:
The patent segments the clock domain crossing function into distinct writer and reader circuits operating in their respective clock domains. Each circuit can maintain its independent clock domain and optimize performance locally, while the segmentation into separate functional blocks allows for controlled interaction through defined interfaces, preventing synchronization issues that would arise from attempting to unify the clock domains.
Data Source
AI summary
An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.