Clock Domain Crossing Verification Scoring
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Solution Overview
Problem
The complexity of modern integrated circuits, particularly at clock domain crossings, leads to challenges in ensuring correct design verification, as existing methods struggle to accurately identify and score clock domain crossings, potentially resulting in synchronization failures and circuit malfunctions.
Innovation Solution
A circuit verifier system that scans integrated circuit descriptions to identify clock domain crossings, calculates a mean time between synchronization failures (MTBF), and assigns scores based on timing information, using libraries of templates to classify and suggest corrections for erroneous crossings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods are used to verify integrated circuits, then the verification process can be performed, but the accuracy of identifying clock domain crossings is insufficient leading to potential synchronization failures
Solution Approach 1:
The verification process is segmented into distinct phases: scanning the circuit description to identify clock domain crossings, calculating MTBF for each crossing, assigning scores based on timing information, and classifying crossings using templates. This segmentation allows each phase to be optimized independently, improving overall verification accuracy.
Solution Approach 2:
The patent introduces an intermediary scoring system that calculates MTBF and assigns numerical scores to clock domain crossings based on timing information. This intermediary mechanism provides a quantitative measure of reliability for each crossing, enabling more accurate identification and classification of critical crossings that may lead to synchronization failures.
2Productivity
If clock domain crossings are not properly handled, then circuit operation can proceed, but synchronization failures may occur resulting in circuit malfunctions
Solution Approach 1:
The system performs preliminary analysis by scanning the circuit description before operation to identify all clock domain crossings and calculate their MTBF values. This preliminary action allows the system to assign scores and classify crossings in advance, enabling proactive identification of potential synchronization failures before they occur during circuit operation.
Solution Approach 2:
The patent implements a feedback mechanism where the calculated MTBF and assigned scores are used to classify clock domain crossings and generate verification results. This feedback loop allows the system to continuously monitor and verify the reliability of clock domain crossings, providing information that can be used to correct potential synchronization issues.
3Reliability
If comprehensive analysis of clock domain crossings is performed, then verification reliability is improved, but the analysis time and computational resources increase
Solution Approach 1:
The system changes the parameter of analysis depth by calculating MTBF values and assigning scores based on timing information for each clock domain crossing. This parameter change enables comprehensive analysis that improves verification reliability while the structured approach to classification using templates helps manage the computational complexity and time required for analysis.
Data Source
AI summary
A circuit verifier having an input interface configured to receive descriptions of integrated circuits and a processing unit configured to scan through a description of an integrated circuit received through the input interface in order to identify clock domain crossings in the circuit and to provide a numerical score for each of the identified clock domain crossings.