Clock Domain Crossing Circuit for Stable Logic Interface Signals
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Solution Overview
Problem
In integrated circuits, particularly in system-on-a-chip (SoC) devices, clock domain crossing (CDC) poses challenges due to differing clock frequencies between logic circuits, leading to difficulties in maintaining synchronized actions across different clock domains.
Innovation Solution
A circuit and method for clock domain crossing that includes a control circuit configured to manage control signals and data signals between master and slave logic circuits operating at different clock frequencies, ensuring signal stability and synchronization through specific circuit segments and protocols, such as the use of flip-flops and AND gates, to prevent metastability and eliminate the need for additional buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional buffers or asynchronous FIFOs are used to manage clock domain crossing, then signal stability and synchronization are improved, but device complexity and space requirements increase
Solution Approach 1:
The patent extracts the essential synchronization function from complex buffer/FIFO structures and implements it using a minimal circuit consisting of only an AND gate and two inverters. This removes unnecessary complexity while retaining the core functionality of maintaining signal stability across clock domains.
Solution Approach 2:
The circuit uses the existing clock signals from both domains to automatically control the timing of signal transfer. The AND gate inherently synchronizes signals by gating them with the appropriate clock edges, eliminating the need for external control logic or complex synchronization mechanisms.
2Reliability
If additional buffers or asynchronous FIFOs are used to manage clock domain crossing, then signal stability and synchronization are improved, but the area occupied on the integrated circuit increases
Solution Approach 1:
The patent extracts the essential synchronization function from complex buffer/FIFO structures and implements it using a minimal circuit consisting of only an AND gate and two inverters. This removes unnecessary complexity while retaining the core functionality of maintaining signal stability across clock domains.
Solution Approach 2:
The patent applies synchronization only at the critical interface point between clock domains using a localized minimal circuit, rather than using extensive buffers or FIFOs throughout the signal path. This concentrates the area usage in the smallest possible region while achieving the required reliability.
3Reliability
If complex protocols and additional circuits are used to manage clock domain crossing, then signal synchronization is improved, but the difficulty of detecting and measuring signal relationships increases
Solution Approach 1:
The patent segments the synchronization function into distinct, simple stages: the first inverter processes the first clock signal, the AND gate performs the gating operation, and the second inverter processes the second clock signal. This segmentation makes each stage's function transparent and easy to detect and measure independently.
Solution Approach 2:
The circuit uses the existing clock signals from both domains to automatically control the timing of signal transfer. The AND gate inherently synchronizes signals by gating them with the appropriate clock edges, eliminating the need for external control logic or complex synchronization mechanisms.
Data Source
AI summary
Systems, circuits, and methods for clock domain crossing for an interface between logic circuits are provided. A circuit is configured to allow an exchange of signals between a first logic circuit clocked using a first clock signal having a first frequency and a second logic circuit clocked using a second clock signal having a second frequency different from the first frequency. The circuit includes a first circuit segment configured to receive a first control signal to select the second logic circuit and a second control signal to indicate an initiation of an access operation, and ensure that the second control signal maintains a relationship with the first control signal based on the second clock signal. The circuit further includes a second circuit segment configured to receive, from the second logic circuit, a third control signal indicating a readiness of the second logic circuit to complete the access operation.