Clock Domain Crossing Verification Using Undefined Value Insertion
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Solution Overview
Problem
Existing verification tools fail to detect clock domain crossing violations between synchronous clock domains, particularly when the fast clock is an integer multiple of the slow clock, leading to potential timing violations that can only be identified during the synthesis phase, and not during design verification.
Innovation Solution
A method that inserts undefined values on slow clock domain signals during fast clock periods when they are not supposed to be captured, using zero-delay verification tools to analyze systems with a slow clock driving a control path and a fast clock driving a data path, ensuring proper sampling and detection of clock domain crossing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If zero-delay verification tools are used for design verification, then verification speed and efficiency are improved, but clock domain crossing violations cannot be detected
Solution Approach 1:
The patent applies preliminary action by inserting undefined values into slow clock domain signals before verification occurs. This pre-conditioning of the test signal allows the zero-delay verification tool to detect clock domain crossing violations that would otherwise be invisible, resolving the contradiction between verification speed and detection accuracy.
2Manufacturing precision
If conservative DDR domain timing is applied to all signals, then timing closure is achieved, but timing violations are introduced in areas not designed for fast DDR clock timing
Solution Approach 1:
The patent applies local quality by differentiating between signals that should receive conservative DDR timing treatment and those that should not. By inserting undefined values only in specific slow clock domain signals and allowing zero-delay simulation for others, the method applies timing constraints locally where needed rather than universally, preventing timing violations in areas not designed for fast clock timing.
3Productivity
If clock domain crossing is not properly handled, then design verification passes, but synthesis phase errors occur
Solution Approach 1:
The patent performs preliminary detection of clock domain crossing violations during the verification phase by inserting undefined values into slow clock domain signals. This early detection prevents undetected errors from propagating to the synthesis phase, resolving the contradiction between verification throughput and design correctness.
4Productivity
If fast clock is used for timing-critical logic, then data transfer bandwidth is increased, but chip layout complexity and physical design difficulty increase
Solution Approach 1:
The patent uses an intermediary approach by introducing a verification mechanism (undefined value insertion) that mediates between the fast clock domain and slow clock domain. This allows the system to maintain high-bandwidth fast clock paths in critical areas while using standard slow clock paths in non-critical areas, with the verification mechanism ensuring proper domain crossing handling, thus reducing overall layout complexity.
Data Source
AI summary
The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violations in device under test designs comprising two different clock domains where the fast clock rate is an integer multiple of the slow clock rate by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainty of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.