Clock Domain Crossing Adapter Using FIFO Buffering for Write Acknowledgments
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Solution Overview
Problem
In electronic systems with master and slave circuitry operating in different clock domains, the lack of timely acknowledgments due to intentionally slowed or stopped clock signals can lead to repeated request cycles, causing applications to appear inoperative without clear error indication, especially in debugging scenarios.
Innovation Solution
A transaction adapter with first and second write FIFO circuits, a read FIFO circuit, and a write acknowledgment control circuit buffers write and read requests and issues acknowledgments to the master circuit independently of the slave circuit's clock signal status, ensuring continuous operation and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If the slave circuit's clock signal is intentionally slowed or stopped for debugging, then debugging capability is improved, but acknowledgment timing deteriorates causing application hang-ups
Solution Approach 1:
The system performs preliminary actions by buffering requests and acknowledgments in FIFO circuits before the slave circuit is ready to process them. The master circuit sends requests that are buffered in the first write FIFO, and acknowledgment buffers (second write FIFO and read FIFO) are prepared in advance to handle the timing mismatch, allowing the slave clock to be slowed or stopped without causing hang-ups.
2Productivity
If the master circuit continuously issues requests expecting timely acknowledgments, then request processing throughput is improved, but system stability deteriorates when slave clock is stopped
Solution Approach 1:
The patent introduces intermediary buffering components (first write FIFO, second write FIFO, and read FIFO) that act as mediators between the master and slave circuits. These buffers decouple the continuous request issuance from the intermittent acknowledgment return, allowing high throughput request processing while maintaining system stability when the slave clock is stopped or slowed.
3Reliability
If acknowledgment is sent after slave circuit processes write request, then data integrity is improved, but master circuit operation deteriorates due to timeout errors
Solution Approach 1:
The system performs preliminary acknowledgment buffering in the second write FIFO and read FIFO before the slave circuit processes and returns the actual acknowledgment. This preliminary action allows the master circuit to continue operating without timeout errors, while data integrity is maintained through the buffered acknowledgment that confirms proper data transfer.
Data Source
AI summary
A circuit arrangement for handling write and read requests between a master circuit and a slave circuit in different clock domains includes first and second write FIFO circuits, a read FIFO circuit, and a write acknowledgment circuit. The first write FIFO circuit is configured and arranged to receive and buffer write addresses of write requests received from a master circuit and addressed to a slave circuit. The second write FIFO circuit is configured and arranged to receive and buffer write data associated with the write addresses of the write requests. The read FIFO circuit is configured and arranged to receive and buffer read addresses of read requests received from the master circuit and addressed to the slave circuit. The write acknowledgment control circuit is configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request.