Clock Domain Data Transfer Using Transition Detection
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Solution Overview
Problem
Existing methods for transferring data signals between clock domains of different frequencies are slow and power-consuming, often requiring handshaking procedures or extra logic components, which are inefficient and undesirable, especially when one clock domain needs to remain active during periods of inactivity.
Innovation Solution
A method that transfers data signals from a slower clock domain to a faster clock domain by detecting transitions in the slower clock domain using detecting means clocked by the faster clock, allowing for immediate re-transfer if a transition occurs within a predetermined period, thereby ensuring safe data transfer without the need for handshaking or additional synchronization components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If handshaking procedures are used to transfer data between clock domains, then data transfer reliability is improved, but transfer time increases and power consumption increases
Solution Approach 1:
The patent extracts the essential synchronization check from the complex handshaking procedure. Instead of using full handshaking with busy flags and multiple cycles, the invention only extracts and checks the critical transition condition in the slower clock domain, eliminating unnecessary synchronization steps while maintaining reliability.
Solution Approach 2:
The patent inverts the traditional handshaking approach by having the faster clock domain initiate the transfer and only re-transfer if a transition is detected in the slower clock domain. This reverses the conventional slow-clock-initiated handshaking protocol, enabling faster transfer times.
2Reliability
If handshaking procedures are used to transfer data between clock domains, then data transfer reliability is improved, but power consumption increases
Solution Approach 1:
The patent extracts only the essential synchronization check from the full handshaking procedure. By removing unnecessary busy flag exchanges and multiple cycle waits, the invention significantly reduces the time the faster clock domain must remain active, thereby lowering power consumption while maintaining transfer reliability.
Solution Approach 2:
The patent implements periodic checking of the slower clock domain transitions at intervals determined by the faster clock. This periodic detection mechanism replaces continuous handshaking, allowing the faster clock domain to enter low-power states more quickly while still ensuring reliable data transfer.
3Reliability
If extra shadow registers are introduced in the slower clock domain, then data transfer reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the synchronization function from the slower clock domain by using detecting means in the faster clock domain to monitor transitions in the slower clock. This eliminates the need for extra shadow registers and complex synchronization logic in the slower clock domain, reducing overall device complexity while maintaining reliability.
Solution Approach 2:
The patent introduces detecting means as an intermediary component in the faster clock domain that monitors the slower clock domain's transitions. This mediator approach replaces the need for shadow registers in the slower clock domain, achieving the same reliability function with simpler logic placement.
4Reliability
If the faster clock domain is kept running during handshaking, then data transfer reliability is ensured, but power consumption increases
Solution Approach 1:
The patent implements periodic detection of slower clock transitions at intervals set by the faster clock. This allows the faster clock domain to perform minimal, periodic checks rather than continuous handshaking, reducing the active duration required for reliable data transfer while maintaining synchronization integrity.
Solution Approach 2:
The faster clock domain performs self-service by using its own clock to detect transitions in the slower clock domain. This eliminates the need for the slower clock domain to actively participate in synchronization protocols, reducing the time both domains must remain active and enabling lower power consumption.
Data Source
AI summary
An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means (2) clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means (2) detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.