Asynchronous Clock Domain Data Transfer via Buffering
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Solution Overview
Problem
Existing methods for transferring data signals between unsynchronized clock domains in digital systems are slow and power-consuming, requiring both domains to be active simultaneously and involving lengthy handshaking procedures, which can lead to data losses and unnecessary power usage, especially when one domain is inactive or operates at a slower frequency.
Innovation Solution
A system that uses flip-flops to store and transfer data signals on positive transitions of the second clock domain, allowing asynchronous transfer without the need for simultaneous activity of both clock domains, and includes mechanisms to activate the second clock domain when necessary, reducing power consumption and transfer time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If handshaking procedure is used to transfer data between clock domains, then data transfer reliability is improved, but power consumption increases and transfer speed decreases
Solution Approach 1:
The patent uses a buffer to store data in advance before the receiving clock domain is ready. The buffer holds the data temporarily, eliminating the need for complex handshaking procedures while ensuring data is available when the receiver becomes active, thus reducing power consumption without sacrificing reliability.
Solution Approach 2:
The patent extracts the handshaking mechanism from the data transfer process by using an independent buffer and clock domain. The buffer operates autonomously, separating the data storage function from the clock synchronization requirement, thereby eliminating the power-consuming handshaking overhead while maintaining transfer reliability.
2Reliability
If handshaking procedure is used to transfer data between clock domains, then data transfer reliability is improved, but transfer speed decreases
Solution Approach 1:
The buffer stores data in advance before the receiving clock domain is ready, eliminating the need for time-consuming handshaking negotiations. Data is prepared and waiting in the buffer, so transfer occurs immediately when the receiver becomes active, significantly improving transfer speed while maintaining reliability through the buffered storage mechanism.
3Reliability
If issuing clock domain is kept active to wait for receiving clock domain, then data transfer reliability is improved, but power consumption increases
Solution Approach 1:
The patent extracts the waiting function from the issuing clock domain by implementing an independent buffer. The buffer remains active and ready to receive data, while the issuing clock domain can enter low-power states. This separation allows reliable data transfer without requiring the issuing domain to remain continuously active, thus reducing power consumption.
Solution Approach 2:
The buffer acts as an intermediary between the issuing and receiving clock domains. It receives data from the issuer and delivers it to the receiver, mediating the transfer without requiring both domains to be simultaneously active. This intermediary mechanism ensures reliable transfer while allowing power savings when domains are inactive.
4Reliability
If handshaking procedure is used, then simultaneous activity of both clock domains is required, but this increases power consumption
Solution Approach 1:
The patent removes the requirement for simultaneous domain activity by extracting the data holding function into a separate buffer. The buffer independently manages data storage and timing, allowing the issuing and receiving clock domains to operate asynchronously without needing to be simultaneously active, thus eliminating the power consumption associated with maintaining both domains in active state.
Data Source
Figure 1
Figure 2
AI summary
An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock domain (2), means (6, 7) for storing the input signal (data_a), and means (12, 13) for transferring the input signal (data_a) to the second clock domain (4) following a transition in the clock signal (ck) of the second clock domain (4).