Clock-Domain Transfer Circuit With Adaptive Edge Sampling
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Solution Overview
Problem
In modern System-on-Chip (SoC) designs with multiple asynchronous clock domains, transferring signals between these domains often results in setup or hold timing violations, leading to meta-stability and functional CDC errors, which are difficult to address early in design cycles and can cause ambiguity in signal capture during testing, especially when clock phase changes occur.
Innovation Solution
A circuit comprising a digital circuit, phase comparator, and data signal synchronization circuit that determines the phase relationship between source and target clock signals, allowing data signal synchronization by switching between sampling on rising or falling edges based on the phase difference, thereby avoiding ambiguity and ensuring accurate timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-flip-flop circuit solution is used for clock domain crossing, then data transfer between clock domains is enabled, but timing ambiguity of 2 clock cycles occurs due to setup/hold time violations
Solution Approach 1:
The patent applies dynamics by making the sampling edge selection adaptive rather than fixed. The circuit dynamically switches between sampling on rising edges or falling edges of the target clock based on real-time phase relationship detection. This dynamic adaptation eliminates the static timing ambiguity inherent in conventional two-flip-flop solutions, resolving the contradiction between enabling data transfer and maintaining timing precision.
Solution Approach 2:
The patent changes the sampling parameter (which clock edge to use) based on the detected phase relationship. By monitoring the phase difference between source and target clocks and adjusting the sampling edge selection accordingly, the system optimizes timing capture accuracy. This parameter adaptation resolves the timing precision issue while maintaining reliable data transfer across clock domains.
2Measurement precision
If a PLL is used to shift clock domains in phase to remove timing ambiguity, then timing precision is improved, but settling time becomes very long (some ms) and one PLL per clock domain crossing is required
Solution Approach 1:
The patent replaces the expensive, time-consuming PLL with a simpler, faster phase detection mechanism. Instead of using a complex PLL that requires milliseconds to settle, the system employs a lightweight phase comparator that instantly determines the phase relationship and adjusts sampling accordingly. This substitution eliminates the lengthy settling time while maintaining timing precision, effectively using a 'cheap short-living' solution compared to the PLL alternative.
Solution Approach 2:
The patent extracts only the essential function needed for timing alignment - phase detection - from the complex PLL system. By separating the phase detection function from the frequency synthesis and locking mechanisms of a PLL, the system achieves timing precision without the overhead of PLL settling time, removing unnecessary complexity while retaining the critical timing alignment capability.
3Device complexity
If static timing analysis is used for clock domain transition, then timing verification is simplified, but it cannot adapt to phase changes when SYNCCLK turns on and off for each test run
Solution Approach 1:
The patent transforms the static timing analysis approach into a dynamic system that adapts to changing phase relationships. By continuously detecting the phase relationship between clock domains and adjusting the sampling edge selection in real-time, the system maintains timing accuracy despite phase changes occurring with each SYNCCLK activation. This dynamic adaptation resolves the contradiction between verification simplicity and adaptability to phase changes.
Data Source
AI summary
The invention concerns a circuit for transferring a data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal synchronized with a source clock signal, and to receive such data by sampling the data signal synchronized with a target clock signal; a phase comparator which is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive data signal transitions that are synchronized with the source clock signal, and to provide a synchronized data signal transitions of which are synchronized with the target clock signal.