On-Chip Clock Domain Characterization for Dynamic Frequency Scaling
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Solution Overview
Problem
As semiconductor manufacturing processes produce chips with varying operating speeds due to manufacturing variability, existing testing and binning methods become complex and costly, especially as chips become more intricate, making it difficult to determine and utilize higher operating speeds effectively.
Innovation Solution
Incorporating on-chip resources and circuitry, such as speed test blocks and ring oscillators, to determine and dynamically adjust the operating speed of chips beyond their nominal specifications, allowing for accurate measurement and adjustment of operating speeds without introducing errors, and providing information to systems for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional testing and binning methods are used to determine operating speeds, then chip speed capability can be identified, but testing complexity and cost increase significantly as chips become more complex
Solution Approach 1:
The chip performs self-testing through on-chip speed test circuits that automatically characterize its own operating speed capabilities without requiring complex external testing equipment. The chip instruments itself with test circuits that measure and report its speed bin during normal operation or manufacturing testing.
Solution Approach 2:
The testing function is extracted from complex external testing equipment and integrated directly into the chip itself through on-chip speed test circuits. This removes the need for sophisticated external test benches and reduces testing complexity while maintaining measurement precision.
2Reliability
If chips are designed for worst-case electrical characteristics to ensure minimum performance, then all chips meet specifications, but faster chips cannot operate at their true higher speeds
Solution Approach 1:
The chip's operating speed is made dynamic rather than static. Instead of being locked to a conservative worst-case speed, the chip can dynamically adjust its operating frequency based on its actual measured capabilities, allowing faster chips to operate at higher speeds while slower chips maintain reliable operation at lower speeds.
Solution Approach 2:
The operating speed parameter is changed from a fixed worst-case value to a variable value determined by actual chip characteristics. Speed test circuits measure the chip's true capabilities and adjust the operating frequency parameter accordingly, enabling each chip to operate at its optimal speed within reliable bounds.
3Device complexity
If on-chip speed test circuits are implemented to enable in-situ testing, then testing complexity is reduced, but chip area and manufacturing cost increase
Solution Approach 1:
The speed test circuits are merged with the functional logic circuits of the chip. Test functionality is combined with operational circuits, allowing the same hardware to serve dual purposes during different phases, thereby minimizing the additional area required for testing functionality.
Solution Approach 2:
The on-chip circuits are designed to be multi-functional, serving both as functional logic during normal operation and as speed test circuits during characterization. This universality reduces the need for dedicated test-only hardware, minimizing area overhead while enabling comprehensive speed testing.
Data Source
AI summary
Chip instrumentation determines, in-situ, an allowable increase over product specification in the operating frequency of at least one clock domain in an integrated circuit for a given set of environmental, power supply and/or functionality constraints. Information on the allowable increase in operating frequency for the at least one clock domain is provided to circuits and/or software to effect change in operating frequency.