Clock Domain Synchronization for Safe Dynamic Frequency Switching
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Solution Overview
Problem
Existing technologies face challenges in synchronizing data transfer between variable clock domains, leading to significant latency and the need for clock frequency changes that require stopping clocks to prevent glitches, which can cause functional errors.
Innovation Solution
A circuit and method that utilize clock circuitry with synchronisation logic to generate pulses for data transfer between clock domains, allowing dynamic frequency changes without stopping clocks, using clock dividers and synchronisation generators to ensure low-latency data transfer and safe clock switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard clock-domain crossing mechanisms are used to transfer data between clock domains, then data transfer bandwidth is sufficient, but latency increases significantly due to metastability resolution and handshake control signals
Solution Approach 1:
The patent introduces a special high-gain flip-flop as an intermediary element that directly couples the two clock domains. This flip-flop acts as a mediator that transfers data signals from the first clock domain to the second clock domain without requiring traditional metastability resolution circuits or handshake protocols, thereby significantly reducing latency while maintaining transfer reliability
Solution Approach 2:
The patent changes the electrical parameter (gain) of the flip-flop to create a special high-gain configuration. By increasing the gain parameter of the flip-flop, the circuit can directly capture and transfer data across clock domains with different frequencies, eliminating the need for complex synchronization mechanisms and reducing transfer latency
2Adaptability or versatility
If clock frequency is changed dynamically, then system adaptability improves, but clocks must be stopped to prevent glitches which causes functional errors
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the clock domain boundaries before frequency changes occur. The synchronization logic detects when both clock domains are aligned at their respective rising edges, and only allows frequency division ratio changes at these synchronized moments. This preliminary synchronization ensures that clock transitions occur at safe points, preventing glitches and maintaining functional correctness during dynamic frequency adaptation
Solution Approach 2:
The patent implements feedback through synchronization logic that continuously monitors the relative phases of both clock domains. The logic provides feedback signals that indicate when clock domains are properly synchronized and ready for frequency changes. This feedback mechanism ensures that frequency division ratios are only changed when conditions are safe, preventing glitches and maintaining system reliability during dynamic frequency changes
3Reliability
If traffic across the interface is stopped during clock frequency changes, then data integrity is maintained, but productivity decreases
Solution Approach 1:
The patent achieves continuity of useful action by allowing data transfer to continue uninterrupted during clock frequency changes. The special high-gain flip-flop maintains data transfer paths active throughout the frequency transition process, and the synchronization logic coordinates clock domain changes in a way that preserves data flow continuity. This eliminates the need to stop traffic during frequency changes, maintaining both data integrity and productivity
Data Source
AI summary
A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data between the first and second circuit portions. The clock circuitry generates a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge, and a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge. A change in the relative frequency is conditional on a coincidence of the first and second control signals. The synchronisation generates the pulses such that there is at least one cycle of the first clock signal between those pulses, and such that there is only one of those pulses per cycle of the second clock signal.