Clock Domain Data Handoff via Phase-Aware Sampling
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Solution Overview
Problem
Current data transfer methods between clock domains require redundant handoffs or handshakes, leading to delays and decreased bandwidth due to the loss of phase information and bit error rates, especially when clock frequencies have a rational relationship but unknown phase alignment.
Innovation Solution
A method and apparatus that utilize a greatest common factor detector to synchronize clock signals, a counter to track skew between clock signals, and a sampling circuit to sample data based on the count value, allowing direct data transfer without relying on FIFO buffers by determining optimal sampling edges and using a blackout window to avoid metastability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIFO buffer is used to transfer data between clock domains, then data transfer reliability is improved, but transfer delay increases and bandwidth decreases
Solution Approach 1:
The patent extracts the phase information tracking mechanism from the traditional FIFO approach and implements it through a counter that tracks the phase relationship between clock domains. This allows direct data transfer without relying on FIFO buffers, eliminating the associated delays while maintaining reliability through phase-aware sampling.
Solution Approach 2:
The patent implements dynamic sampling timing based on the current phase relationship between clock domains. The counter value determines which clock edge (rising or falling) of the destination clock should be used for sampling, allowing the system to adapt to changing phase conditions and optimize transfer timing in real-time.
2Reliability
If redundant handshakes are used for data transfer, then data transfer accuracy is improved, but transfer speed decreases
Solution Approach 1:
The patent performs preliminary tracking of the phase relationship between clock domains using a counter that continuously monitors the skew between clocks. This preliminary information is then used to determine the optimal sampling timing in advance, eliminating the need for redundant handshakes during the actual data transfer process.
Solution Approach 2:
The system uses feedback from the phase tracking counter to dynamically adjust the sampling timing. The counter value indicates whether the destination clock's rising or falling edge should be used for sampling, creating a closed-loop system that maintains accuracy without requiring redundant verification handshakes.
3Device complexity
If phase information is lost during data transfer, then device complexity is reduced, but bit error rate increases
Solution Approach 1:
The patent introduces a counter as an intermediary mechanism that tracks the phase relationship between clock domains. This intermediary provides the necessary phase information without requiring complex synchronization protocols, enabling direct data transfer while maintaining low bit error rates through phase-aware sampling decisions.
4Reliability
If FIFO buffer is used for data transfer, then data transfer reliability is improved, but interface bandwidth decreases
Solution Approach 1:
The patent removes the FIFO buffer from the data transfer path and replaces it with a phase-tracking counter that enables direct sampling. This extraction of the buffering mechanism eliminates the bandwidth bottleneck while maintaining reliability through phase-aware sampling, allowing faster data transfer rates.
Data Source
AI summary
A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.