Asynchronous Clock Domain Hierarchy Separation for Multi-Voltage Optimization
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Solution Overview
Problem
Legacy intellectual property (IP) electronic modules designed without asynchronous clock boundaries fail to effectively manage power consumption across multiple clock domains, leading to inefficiencies in dynamic and static power savings.
Innovation Solution
The method involves grouping logic for each clock domain into separate hierarchies, performing logic cloning, level shifter and isolation cell insertion, and register grouping to isolate timing paths within these hierarchies, allowing for independent optimization of voltage and frequency across distinct voltage islands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If logic is grouped into separate hierarchies for each clock domain, then power consumption is reduced through independent voltage optimization, but device complexity increases due to logic cloning and hierarchy creation
Solution Approach 1:
The design is segmented into multiple logical hierarchies, each corresponding to a specific clock domain. This segmentation allows independent voltage optimization for each domain, reducing overall power consumption while managing complexity through structured organization
Solution Approach 2:
Voltage parameters are changed and optimized independently for each logical hierarchy corresponding to different clock domains. By adjusting voltage levels per domain rather than uniformly across the entire design, power consumption is reduced while maintaining performance requirements
2Loss of energy
If voltage islands are created for each asynchronous clock domain, then leakage power is reduced through independent voltage control, but manufacturing complexity increases due to isolation cell insertion
Solution Approach 1:
The design is divided into separate voltage islands, each corresponding to an asynchronous clock domain. This segmentation enables independent voltage control for leakage power reduction, with manufacturing complexity managed through systematic isolation cell insertion
Solution Approach 2:
Isolation cells are inserted as intermediary elements between different voltage islands. These cells facilitate voltage domain separation and control, enabling leakage power reduction while maintaining manufacturability through standardized isolation mechanisms
3Productivity
If timing paths are isolated within specific hierarchies, then power management is optimized through independent voltage domain mapping, but logic complexity increases due to required logic cloning
Solution Approach 1:
Timing paths are segmented and confined within specific logical hierarchies corresponding to their clock domains. This isolation enables efficient independent power management and voltage domain mapping, with logic cloning used strategically to maintain functionality while reducing overall power consumption
Data Source
AI summary
This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.