Clock Domain Management for Configurable IC Clock Distribution
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Solution Overview
Problem
Modern large-scale integrated circuits face complexity in managing interconnections between multiple clock sources and a large number of configurable circuits, particularly in FPGAs and PLDs, where the number of possible clock/configurable circuit pairings becomes unmanageable due to the increased size and complexity of functionalities.
Innovation Solution
The integration of a clock management block (CMB) that configurably distributes multiple clocks to multiple clock domains, synchronizes control signals, and aligns sub-cycle operations within each domain, using phase-lock loops and master-slave CMB arrangements to ensure efficient clock distribution and operation across the IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock sources are provided to support different functionalities in an IC, then the adaptability and functionality of the IC are improved, but the device complexity and interconnection management become unmanageable
Solution Approach 1:
The patent divides the IC into multiple clock domains, where each clock domain is a segmented group of circuit elements that share a common clock source. This segmentation allows independent management of clock distributions within each domain, making the overall complex interconnection system manageable by breaking it into smaller, organized units.
Solution Approach 2:
The patent introduces clock domain assignment logic as an intermediary component that manages the mapping between configurable circuits and clock sources. This intermediary automatically handles the complex interconnection management by assigning circuits to appropriate clock domains based on configuration parameters, eliminating the need for manual management of multiple clock sources.
2Adaptability or versatility
If configurable circuits are paired with multiple possible clock sources, then the adaptability of the IC is improved, but the device complexity increases significantly
Solution Approach 1:
The patent creates a universal clock domain assignment mechanism that can handle any pairing of configurable circuits with clock sources through a standardized interface. The clock domain assignment logic provides multi-functional capability to manage different configuration scenarios without requiring separate interconnection paths for each possible circuit-clock pairing.
Solution Approach 2:
The patent implements dynamic clock domain assignment where the mapping between circuits and clock sources can be changed through configuration parameters. This dynamic approach allows the IC to adapt its clock distribution topology based on operational requirements, providing configurability without permanent complex interconnections for all possible pairings.
3Manufacturing precision
If clock distribution networks are physically designed into the IC prior to fabrication, then the manufacturing precision is improved, but the adaptability and ease of operation are reduced
Solution Approach 1:
The patent performs preliminary action by establishing the physical clock distribution network infrastructure during IC fabrication with predetermined timing characteristics. However, it delays the actual clock domain assignments and circuit-to-clock mappings until after fabrication, using configuration parameters to dynamically assign circuits to clock domains. This allows the physical network to be optimized for timing while the logical assignments remain flexible and configurable.
Data Source
AI summary
A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.