Clock Domain Inference for Power Optimization in Behavioral Synthesis
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Solution Overview
Problem
Current high-level synthesis (HLS) technologies face challenges in optimizing clock gating for integrated circuits, leading to inefficient power consumption and increased dynamic power dissipation due to the lack of effective methods for inferring and assigning clock domains based on conditional statements and dependency relationships in behavioral descriptions.
Innovation Solution
The proposed solution involves a behavioral synthesis engine that analyzes conditional statements and their dependency relationships to infer potential clock domains, enabling optimized clock gating structures and power management by selectively disabling circuit portions with static inputs and outputs, thereby reducing power consumption through the use of gated clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are provided to all circuit portions continuously, then circuit operation reliability is improved, but power consumption increases
Solution Approach 1:
The circuit is divided into multiple clock domains based on conditional statements and dependency relationships. Each clock domain receives clock signals independently, allowing selective gating of clock signals to specific circuit portions based on their operational requirements, thereby reducing overall power consumption while maintaining reliability where needed.
Solution Approach 2:
Clock gating mechanisms are implemented to dynamically control clock signal distribution. The clock signals are selectively enabled or disabled based on runtime conditions and dependency relationships, allowing the circuit to adapt power consumption to actual operational needs while maintaining reliability during active periods.
2Use of energy by moving object
If clock gating is implemented without inferring clock domains from conditional statements, then power consumption is reduced, but circuit functionality deteriorates
Solution Approach 1:
The system analyzes conditional statements and dependency relationships to infer appropriate clock domains. This feedback mechanism ensures that clock gating decisions are based on actual circuit logic and data flow requirements, preventing functional deterioration while achieving power savings through informed clock signal management.
Solution Approach 2:
Clock domains are inferred and assigned before circuit operation based on static analysis of conditional statements and dependency relationships. This preliminary action ensures that clock gating strategies are pre-configured to match the circuit's logical structure, guaranteeing functionality while enabling power optimization.
3Device complexity
If clock domains are not inferred from dependency relationships, then circuit complexity is reduced, but power optimization capability deteriorates
Solution Approach 1:
The synthesis process automatically infers clock domains by analyzing dependency relationships within the circuit's conditional statements. This self-service approach extracts timing and power optimization information directly from the circuit's logical structure without requiring external annotation or manual configuration, achieving power optimization with minimal additional complexity.
Data Source
AI summary
Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements.