Clock-Domain Signal Checking with Delayed Lockstep Redundancy
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Solution Overview
Problem
In integrated circuits with multiple clock domains, maintaining a fixed temporal delay between primary and redundant signals across clock domain boundaries is challenging due to misaligned clock frequencies and phases, which complicates error detection and reduces the effectiveness of lockstep redundancy mechanisms.
Innovation Solution
The apparatus includes a first portion in one clock domain with a primary and redundant interface, and a second portion in another clock domain with corresponding interfaces, where a checking signal is generated based on the primary signal and supplied with a predetermined time delay to recreate the lockstep mechanism, enabling error checking across the clock domain boundary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lockstep redundancy mechanism is used across clock domain boundaries, then error detection capability is improved, but maintaining fixed temporal delay between primary and redundant signals becomes difficult due to misaligned clock frequencies and phases
Solution Approach 1:
The patent applies preliminary action by generating the second checking signal in advance within the second clock domain based on the primary signal, before the actual data transmission occurs. This pre-generated checking signal is stored and then supplied with the predetermined time delay to recreate the lockstep mechanism, allowing error detection to function properly despite clock domain misalignment.
Solution Approach 2:
The patent introduces an intermediary mechanism by using a checking signal generation circuit that operates independently within the second clock domain. This intermediary circuit generates checking signals based on the primary signal and supplies them with the correct time delay, acting as a mediator that bridges the clock domain boundary and enables error detection without requiring direct synchronization between the misaligned clock domains.
2Reliability
If checking signal is generated and supplied with predetermined time delay to recreate lockstep mechanism, then functional safety is improved, but device complexity increases due to additional checking circuitry
Solution Approach 1:
The patent applies copying by generating a second checking signal that is a copy or derivative of the primary signal, created within the second clock domain. This copied signal is then supplied with the predetermined time delay to the second redundant interface, enabling error checking functionality without requiring complete duplication of the entire system, thus balancing functional safety with manageable device complexity.
Data Source
AI summary
An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.