Clock-Domain Control Signal Transfer With Reduced Metastability Delay
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Solution Overview
Problem
Conventional metastability measure circuits fail to correctly receive control signal pulses and introduce significant delays when operating between semiconductor chips and FPGAs with different clock frequencies, leading to oscillation and signal loss due to differing clock frequencies.
Innovation Solution
A transmission apparatus and method that synchronizes sending and receiving parts with different clock frequencies by inverting signal levels in response to pulse inputs, using a combination of high-speed and low-speed clock operating parts and EXOR circuits to select and generate pulse signals, thereby stabilizing signal transmission and reducing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a conventional metastability measure circuit with series-connected flip-flops is used, then the oscillation phenomenon is suppressed and signal stability is improved, but control signal pulse loss or duplication occurs and significant delay is generated when clock frequencies differ between transmission and reception sides
Solution Approach 1:
The patent applies dynamics by making the number of flip-flops in the metastability measure circuit adjustable rather than fixed. The control unit dynamically configures the circuit structure based on clock frequency relationships: using one flip-flop when clock frequencies are equal, two flip-flops when frequencies differ (to prevent pulse loss/duplication), and adjusting the configuration to minimize delay when the receiving clock frequency is lower than the sending clock frequency. This dynamic adaptation resolves the contradiction between signal stability and control signal reception accuracy.
2Stability of the object's composition
If the conventional metastability measure circuit is used with FPGA on the reception side having lower clock frequency, then metastability is addressed, but the control signal delay increases significantly (two clock cycles)
Solution Approach 1:
The patent dynamically adjusts the metastability measure circuit configuration based on the receiving clock frequency being lower than the sending clock frequency. The control unit configures the circuit to use an odd number of flip-flops (typically one or three) in this scenario, which reduces the delay to 0.5-1.5 clock cycles compared to the conventional two-cycle delay. This dynamic reconfiguration resolves the contradiction between maintaining signal stability and reducing time loss.
3Adaptability or versatility
If different operation clock frequencies are used between semiconductor chip and FPGA, then system flexibility and adaptability are improved, but metastability occurs and control signal transmission reliability deteriorates
Solution Approach 1:
The patent maintains system flexibility by allowing different clock frequencies between semiconductor chip and FPGA while dynamically adjusting the metastability measure circuit configuration to ensure reliable control signal transmission. The control unit monitors clock frequency relationships and automatically configures the appropriate number of flip-flops (one, two, or three) to prevent metastability and ensure accurate pulse reception, thus resolving the contradiction between adaptability and reliability.
Solution Approach 2:
The patent introduces a control unit as an intermediary that manages the metastability measure circuit configuration. This control unit acts as a mediator between the semiconductor chip and FPGA with different clock frequencies, dynamically adjusting the circuit to ensure reliable signal transmission while maintaining system flexibility. The control unit configures the appropriate number of flip-flops based on clock frequency relationships, resolving the reliability issue without sacrificing adaptability.
Data Source
AI summary
A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.