Clock-Domain Verification of Metastable Data Propagation
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Solution Overview
Problem
Current logic verification methods for semiconductor integrated circuits with multiple clock domains fail to accurately account for metastable conditions, leading to missed verification issues due to the complexity of data propagation across clock domains, resulting in inaccurate assessment of input patterns and potential erroneous operations.
Innovation Solution
A verification support system that includes a detector to identify data fluctuations in the transmitter clock domain and an identification unit to determine if these fluctuations propagate to the output of combinational logic in the receiver clock domain, allowing for precise analysis of metastable condition effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If logic verification is performed by changing the receiver FF model to simulate metastable conditions, then verification accuracy for metastable conditions is improved, but analysis of failure factors becomes difficult and computation cost increases
Solution Approach 1:
The verification process is segmented into two distinct phases: (1) ordinary logic verification using standard FF models to check basic functionality, and (2) metastable condition verification using specialized metastable FF models. This segmentation allows each phase to focus on specific aspects without unnecessary complexity, resolving the contradiction between verification accuracy and model complexity.
Solution Approach 2:
A detector is introduced as an intermediary component that monitors data fluctuations at the output of the receiver FF. This detector acts as a mediator between the metastable FF model and the verification process, enabling accurate detection of metastable effects without requiring complex modifications to the entire verification system.
2Measurement precision
If data propagation is traced from transmitter clock domain to receiver clock domain to assess input pattern suitability, then verification accuracy is improved, but computation cost increases significantly
Solution Approach 1:
The system performs preliminary detection of data fluctuations at the output of the receiver FF before conducting full propagation tracing. By identifying potential metastable conditions early through the detector, the system can avoid unnecessary comprehensive propagation analysis, thus reducing computation time while maintaining verification accuracy.
Solution Approach 2:
Instead of always performing complete end-to-end propagation tracing, the system applies partial action by using the detector to identify cases where metastable conditions occur. Only in these detected cases is full propagation tracing performed to assess input pattern suitability, significantly reducing overall computation time while maintaining accuracy.
3Device complexity
If only the output terminal of the semiconductor integrated circuit is observed, then device complexity is reduced, but verification accuracy decreases due to inability to identify data propagation paths
Solution Approach 1:
The verification system applies local quality by placing the detector specifically at the output of the receiver FF, which is the critical location for detecting metastable conditions. This targeted approach provides high verification accuracy at the most important point without requiring complex observation of the entire circuit, thus resolving the contradiction between complexity and accuracy.
4Ease of operation
If only change in input data is observed to assess input pattern suitability, then measurement simplicity is improved, but verification accuracy decreases due to missed propagation effects through combinational logic
Solution Approach 1:
The detector serves as an intermediary that bridges the gap between simple input observation and accurate propagation detection. By monitoring the output of the receiver FF, the detector captures the actual effect of data fluctuations after they have passed through the combinational logic, providing accurate verification information without requiring complex analysis of internal propagation paths.
Data Source
AI summary
A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock. The system includes an identification unit to identify whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of logic gates of the receiver clock domain to combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic.