Clock Domain Partitioning via Integer Linear Programming

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Solution Overview

Problem

Conventional methods for clock domain partitioning in programmable integrated circuits (ICs) fail to detect infeasible solutions and often cannot determine a feasible partitioning that adheres to clock domain constraints, leading to impractical implementations.

Innovation Solution

A computer-implemented method using integer linear programming (ILP) to partition circuit designs into clock domains by defining objective functions and constraints, including penalty terms for distance and timing criticality, and error variables to manage excessive global clocks, ensuring compliance with clock domain constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional methods for clock domain partitioning are used, then the implementation process is simple, but the method fails to detect infeasible solutions and cannot determine feasible partitioning

Engineering Contradiction:

Improvedetection of feasible solutionsVSAvoidcomplexity of partitioning method

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces conventional heuristic or manual clock domain partitioning methods with an integer linear programming (ILP) framework. This mathematical optimization approach systematically models the partitioning problem using objective functions and constraints, enabling automatic detection of feasible and infeasible solutions through computational solvers, thereby improving reliability without requiring complex manual intervention

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces error variables as intermediaries between the clock domain constraints and the objective function. These error variables quantify the degree of constraint violation, allowing the ILP solver to detect infeasible solutions and provide debugging information about which constraints are violated, thus improving detection capability while maintaining a structured approach

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If clock domain constraints are strictly enforced, then the partitioning is feasible and reliable, but the solution may not exist for certain circuit designs

Engineering Contradiction:

Improvefeasibility of partitioningVSAvoidapplicability to all circuit designs

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements a feedback mechanism through the ILP solver that detects when no feasible solution exists. When the solver determines that the constraints cannot be satisfied, it returns an infeasible result with debugging information indicating which constraints cause the conflict. This feedback allows designers to understand why a partitioning is impossible and modify their circuit design or constraints accordingly, maintaining reliability while adapting to different circuit configurations

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent allows flexible modification of clock domain constraints as parameters. The ILP framework can accommodate different numbers of global clocks per region, different clock region definitions, and varying circuit topologies. By treating constraints as adjustable parameters rather than fixed rules, the method adapts to different circuit designs while maintaining strict enforcement of the chosen constraints, ensuring feasibility when possible and clear identification when not possible

Inventive Principle:

Principle #35Parameter changes

3Reliability

If the number of global clocks per clock region is limited, then the clock domain partitioning is valid, but the placement of components becomes more difficult

Engineering Contradiction:

Improvevalidity of clock domain partitioningVSAvoidease of component placement

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent performs preliminary action by automatically generating an initial placement of components before applying the clock domain constraints. The ILP framework first assigns components to clock regions based on availability and then systematically redistributes them to satisfy the maximum clock constraint. This two-stage approach maintains ease of manufacture by providing a starting point while ensuring validity through automated constraint satisfaction

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces dynamics by allowing the component placement to be adjusted and optimized within the ILP framework. Rather than a static placement, the system dynamically redistributes components across clock regions based on the constraints and objective functions. This dynamic optimization maintains the validity of the clock domain partitioning while finding placement solutions that are as easy to manufacture as possible, balancing constraint satisfaction with placement simplicity

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8091060B1Clock domain partitioning of programmable integrated circuits

Publication Date: 2012.01.03 XILINX INC

AI summary

A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC. The method can include storing an objective function and determining a result indicating whether a feasible solution exists for clock domain partitioning of the circuit design by minimizing the objective function subject to the plurality of constraints. The result can be output.