Clock Domain Synchronization via Phase Estimation
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Solution Overview
Problem
Traditional periodic synchronizers for clock domains face limitations such as significant area overhead and delay due to the use of asynchronous FIFOs, which incur high latency and probability of synchronization failure.
Innovation Solution
A system and method for determining safe sampling times in clock domains by calculating phase estimates based on relative frequency and phase relationships, allowing for the generation of sampled signals without the need for asynchronous FIFOs, thereby reducing latency and synchronization failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous FIFOs are used for synchronization, then signals can be transferred between clock domains, but area overhead increases significantly
Solution Approach 1:
The patent extracts the essential synchronization function from the complex asynchronous FIFO structure, implementing only the necessary phase estimation and sampling timing determination logic. This removes the bulky FIFO memory while retaining the core synchronization capability through phase-based sampling time selection.
Solution Approach 2:
The patent changes the synchronization approach from data-based (FIFO buffering) to parameter-based (phase estimation and sampling timing calculation). By estimating the phase relationship between clock domains and determining safe sampling times based on this phase information, the system achieves synchronization without requiring large buffer memories.
2Reliability
If asynchronous FIFOs are used for synchronization, then signals can be transferred between clock domains, but latency increases due to multiple synchronization cycles
Solution Approach 1:
The patent performs preliminary phase estimation between clock domains before actual data transfer. By calculating the phase relationship in advance and determining safe sampling times beforehand, the system eliminates the need for multiple sequential synchronization cycles, reducing latency to essentially one clock cycle.
Solution Approach 2:
The patent introduces phase estimation and sampling timing determination as intermediary mechanisms between the source and destination clock domains. This intermediary layer provides direct timing information that enables single-cycle synchronization, replacing the multi-cycle handshaking required by traditional FIFO-based approaches.
3Ease of operation
If asynchronous FIFOs are used for synchronization, then signals can be transferred between clock domains, but the probability of synchronization failure increases
Solution Approach 1:
The patent implements feedback through phase estimation, continuously monitoring and calculating the phase relationship between clock domains. This feedback mechanism allows the system to adaptively determine safe sampling times based on actual phase conditions, reducing the probability of synchronization failure compared to fixed FIFO-based timing.
4Loss of time
If phase estimation is used for synchronization, then latency is reduced, but device complexity increases due to phase calculation logic
Solution Approach 1:
The patent replaces the mechanical FIFO buffering approach with a computational phase estimation system. Instead of physically storing and sequentially accessing data through FIFO stages, the system uses arithmetic calculations to estimate phase relationships and determine sampling times, achieving faster synchronization despite the added computational logic.
Data Source
AI summary
A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.