Clock-Domain Interface Pointer Synchronization During Reset
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Solution Overview
Problem
Interface devices operating under different clock domains can experience malfunctions during reset operations due to asynchronous communication, leading to the reading or writing of invalid data.
Innovation Solution
An interface system that includes a first and second interface device with buffers, where the write and read pointers are compared and updated based on a reset signal, incorporating data bits to indicate the reset state, thereby synchronizing operations across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous interface is used between master and slave with different clock domains, then the interface can operate with different clocks, but malfunction occurs during reset operation due to pointer desynchronization
Solution Approach 1:
The patent applies preliminary action by detecting the reset state of the write pointer before the read pointer updates its value. The read pointer includes a reset detection unit that checks whether the write pointer is in reset state before performing update operations, preventing malfunction by anticipating and avoiding the harmful condition of desynchronization during reset operations
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a reset detection unit and control logic that mediates between the write pointer (from slave device) and the read pointer (in master device). This intermediary detects the reset state and controls the update timing of the read pointer, ensuring synchronized operation across different clock domains during reset operations
2Productivity
If read pointer is updated without checking write pointer reset state, then update speed is fast, but invalid data may be read or written causing malfunction
Solution Approach 1:
The read pointer update operation performs preliminary detection of the write pointer's reset state before executing the update. The reset detection unit checks the reset condition in advance, and only allows update when the write pointer is not in reset state, preventing invalid data access while maintaining efficient operation
Solution Approach 2:
The patent implements feedback by using the reset state information from the write pointer to control the read pointer update operation. The control logic receives feedback about the write pointer's reset state and adjusts the read pointer update timing accordingly, creating a closed-loop control system that prevents malfunction
Data Source
AI summary
An interface system may include a first interface device and a second interface device. The first interface device may include a first buffer. The second interface device may include a second buffer. The first interface device may compare a write pointer of the first buffer, which corresponds to the second interface device, with a read pointer of the first buffer, which corresponds to the first interface device, and update the read pointer, based on the comparison result. Each of the write pointer of the first buffer and the read pointer of the first buffer may include data bits indicating an address of the first buffer and a data bit indicating a reset signal. The first interface device may selectively update the read pointer according to the reset signal of the write pointer of the first buffer.