Clock-Domain Pulse Synchronizer for Metastability-Safe Signal Transfer
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Solution Overview
Problem
Existing signal transfer methods between different clock domains in system-on-chip (SoC) designs face challenges in synchronizing signals across domains with varying clock frequencies, leading to potential metastability and data loss due to unknown worst-case clock ratios and phase differences.
Innovation Solution
A signal transfer circuit comprising a first pulse generation circuit, a hold flip-flop circuit, a clocked synchronizer circuit, and a second pulse generation circuit, which generates and synchronizes data pulses across clock domains, ensuring reliable transfer irrespective of clock frequency ratios and phase differences, using a combination of flip-flops and logical gates to manage clock signals and data pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronizing circuits are used to transfer signals between clock domains, then signal transfer reliability may be improved, but the circuit complexity increases and cannot handle unknown worst-case clock ratios and phase differences
Solution Approach 1:
The patent introduces an intermediary pulse generation mechanism that converts data signals into pulses synchronized with the destination clock domain. The pulse generation circuit acts as a mediator between source and destination clock domains, using destination clock edges to trigger pulse generation, thereby eliminating the need for complex traditional synchronizers while handling unknown clock ratios and phase differences.
Solution Approach 2:
The patent changes the parameter representation of data by converting continuous data signals into discrete pulses timed to destination clock edges. This parameter transformation allows the system to handle any clock frequency ratio and phase difference without requiring pre-knowledge of clock relationships, simplifying the circuit while maintaining reliability.
2Device complexity
If signals are transferred without synchronization between different clock domains, then circuit complexity is reduced, but metastability and data loss occur
Solution Approach 1:
The patent employs periodic action by generating pulses only at destination clock edges. This periodic synchronization mechanism ensures that data transfer occurs at regular intervals aligned with the destination clock, preventing metastability and data loss while maintaining relatively simple circuitry compared to traditional continuous synchronization approaches.
Solution Approach 2:
The pulse generation circuit is self-synchronized to the destination clock domain, automatically adapting to any clock frequency ratio or phase difference without external control. The circuit serves itself by using destination clock edges to trigger pulse generation, eliminating the need for complex external synchronization control while ensuring reliable data transfer.
Data Source
AI summary
In certain embodiments, a circuit for transferring signals from a source clock domain to a destination clock domain comprises a first pulse generation circuit, a hold flip-flop circuit, a clocked synchronizer circuit and a second pulse generation circuit. The first pulse generation circuit, operable in the source clock domain, generates a source data pulse from a source data signal. The hold flip-flop circuit, operable in the source clock domain, is configured to hold the source data pulse. The clocked synchronizer circuit, operable in the destination clock domain, samples the source data pulse received from the hold flip-flop circuit, where source data pulse held at the output of the hold flip-flop circuit is cleared when the source data pulse is sampled by the clocked synchronizer circuit. The second pulse generation circuit, operable in the destination clock domain, is configured to generate a destination data pulse from the sampled source data pulse.