Clock-Domain Interface Circuit for Low-Latency Register Transfer
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Solution Overview
Problem
Transferring data between circuits operating in different clock domains, especially from high-speed to low-speed domains, results in significant data latency and increased system power consumption due to synchronization challenges and the need for handshaking protocols, which inhibit high-bandwidth closed-loop control applications.
Innovation Solution
The implementation of interface circuits that include a resettable synchronizer, pulse generator, and dual flip-flop circuits to synchronize data transfers between high-speed and low-speed clock domains, allowing for back-to-back write operations without acknowledgment and minimizing data latency by resetting prior pending write requests and providing synchronized start and read enable signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If handshaking schemes using request-acknowledge protocol are used to synchronize data transfer between high-speed and low-speed clock domains, then data synchronization reliability is improved, but data latency increases significantly
Solution Approach 1:
The patent extracts the acknowledgment requirement from the data transfer process. Instead of requiring an acknowledgment signal to confirm each write operation completion, the system uses a simple request signal that triggers the transfer. The interface circuit handles synchronization independently, eliminating the need for complex handshaking while maintaining reliability through the use of synchronized clocks and controlled data latching.
Solution Approach 2:
The patent implements preliminary synchronization of the request signal to the low-speed clock domain before initiating the data transfer. The interface circuit pre-aligns the timing of the write request with the low-speed clock cycles, ensuring that data is transferred at the appropriate moment without requiring post-transfer acknowledgment. This preliminary timing alignment resolves the contradiction by ensuring reliable transfer without the latency of back-and-forth handshaking.
2Productivity
If frequent data writes are performed from high-speed CPU to low-speed peripheral register, then control bandwidth is improved, but data synchronization complexity increases
Solution Approach 1:
The patent introduces an interface circuit as an intermediary between the high-speed CPU and low-speed peripheral. This intermediary circuit handles all the synchronization complexity internally, including clock domain crossing and data latching. The CPU simply issues write requests without needing to manage synchronization timing, while the interface circuit mediates the actual data transfer at the appropriate low-speed clock cycles. This resolves the contradiction by hiding synchronization complexity from the high-speed processor while maintaining high control bandwidth.
Solution Approach 2:
The interface circuit performs self-service by autonomously managing the data transfer synchronization without requiring CPU intervention. Once the CPU issues a write request, the interface circuit independently synchronizes the request to the low-speed clock domain, latches the data at the correct timing, and completes the transfer. This self-managing approach allows frequent writes from the high-speed CPU without increasing synchronization complexity for the processor.
3Reliability
If multiple reads are performed with comparison to ensure data stability, then data read reliability is improved, but system power consumption increases
Solution Approach 1:
The patent replaces the mechanical approach of multiple sequential reads with a single read operation. The interface circuit uses clock domain synchronization and a single latching event to ensure data stability, eliminating the need for multiple reads and comparisons. The synchronized single read achieves the same reliability as multiple reads but with significantly lower power consumption since the CPU and peripheral circuits perform fewer read cycles.
Data Source
AI summary
Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.