Clock Domain Segmentation for Jitter Reduction in Integrated Circuits
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Solution Overview
Problem
Modern integrated circuits (ICs) face significant jitter issues due to the simultaneous switching of synchronous circuit elements, which generates large current pulses that cause fluctuations in the power supply voltage, leading to reduced performance.
Innovation Solution
The method involves assigning synchronous circuit elements to different groups based on a balancing criterion and clocking them using distinct clock signals, effectively transforming a single clock domain into multiple clock domains, thereby reducing the number of elements switching simultaneously and minimizing current pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If synchronous circuit elements are clocked using a single clock signal, then circuit operation is simplified and coordinated, but large current pulses are generated causing voltage fluctuations and jitter
Solution Approach 1:
The patent divides a single clock domain into multiple clock domains by partitioning synchronous circuit elements into different groups, each clocked by separate clock signals. This segmentation reduces the number of elements switching simultaneously within each domain, thereby reducing current pulse magnitude and resulting voltage fluctuations that cause jitter.
Solution Approach 2:
The patent employs multiple clock signals with different phases to periodically stagger the switching operations of circuit elements. By offsetting the clock edges across different groups, elements switch at different times rather than simultaneously, distributing the current draw over time and reducing peak current pulses.
2Object-affected harmful factors
If multiple clock domains are created to reduce jitter, then voltage fluctuation and jitter are reduced, but circuit design and synchronization become more complex
Solution Approach 1:
The patent creates clock domains that can be universally applied to different groups of circuit elements using standardized clock signal distribution and control mechanisms. This multi-functional approach allows the same clocking strategy to be applied across various parts of the circuit, reducing design complexity through reuse of proven clock domain structures.
Data Source
AI summary
Reducing jitter in a circuit design includes selecting a plurality of circuit elements of a circuit design clocked using a first clock signal and assigning, using a processor, the plurality of circuit elements to different ones of a plurality of groups according to a balancing criterion. The circuit elements assigned to a first group of the plurality of groups are clocked using the first clock signal. The circuit elements assigned to a second group of the plurality of groups are clocked using a second clock signal different from the first clock signal.