Clock Domain Synchronization for Low-Latency Data Transfer
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Solution Overview
Problem
Existing clock-controlled circuitry faces challenges in efficiently transferring data, such as audio data, between different clock domains, leading to potential errors and increased latency due to unpredictable phase relationships between clock signals.
Innovation Solution
The implementation of clock-controlled circuitry with at least two domains, where one domain operates as a master and the other as a slave, with the slave domain adjusting its timing to maintain a phase relationship within specified bounds by receiving a synchronization signal and re-setting its timing if the phase relationship deviates, ensuring minimal errors and reduced latency during data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between clock domains with different frequencies and phases, then data transfer capability is improved, but timing errors and latency increase
Solution Approach 1:
The slave signal generator continuously monitors the phase relationship between the first and second repetitive signals and provides feedback by resetting its timing when the phase relationship deviates from specifications. This closed-loop feedback mechanism maintains timing accuracy despite operating in different clock domains with varying frequencies and phases.
Solution Approach 2:
The patent introduces an intermediary phase relationship monitoring and control mechanism between the master and slave signal generators. This intermediary layer translates the master clock's phase information and adjusts the slave clock's timing accordingly, enabling reliable data transfer across clock domain boundaries without direct coupling.
2Measurement precision
If the phase relationship between clock domains is continuously monitored and adjusted, then timing precision is improved, but system complexity increases
Solution Approach 1:
The slave signal generator performs self-service by autonomously monitoring its own phase relationship with the master signal and automatically resetting its timing when deviations occur. This self-monitoring and self-correction capability reduces the need for external control complexity while maintaining high phase relationship precision.
Solution Approach 2:
The patent merges the functions of phase monitoring, comparison, and timing adjustment into a single integrated control mechanism within the slave signal generator. By combining these functions rather than implementing them as separate components, the system achieves high measurement precision without proportionally increasing overall system complexity.
Data Source
AI summary
Clock-controlled circuitry organised into at least first and second clock domains, the first clock domain configured to operate based on a first clock signal and the second clock domain configured to operate based on a second clock signal, wherein: the first clock domain comprises a first signal generator operable to generate a first repetitive signal synchronised to the first clock signal; the second clock domain comprises a second signal generator operable to generate a second repetitive signal synchronised to the second clock signal; the first signal generator is operable, when operating in master mode, to output to the second signal generator a first synchronisation signal indicative of a phase of the first repetitive signal; and the second signal generator is operable, when operating in slave mode, to: set a timing of the second repetitive signal relative to the second clock signal based on the first synchronisation signal so that the second repetitive signal is set to have a phase relationship with the first repetitive signal which then meets a slave specification; and re-set the timing of the second repetitive signal relative to the second clock signal if it is determined that the phase relationship has changed such that it no longer meets the slave specification.