Hierarchical Clock Domain Synchronization for Nanosecond Precision

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Solution Overview

Problem

Current clock synchronization methods in mobile bearer networks, such as those using the IEEE 1588 protocol, suffer from low precision due to factors like crystal oscillator stability, timestamp precision, and long clock paths, leading to potential channel establishment failures during handovers.

Innovation Solution

A hierarchical multi-clock-domain synchronization method where each node device determines a master clock using a best master clock algorithm, allowing for high-precision synchronization within its domain and reducing error accumulation from long transmission paths, while also enabling dynamic adjustment of clock domains for improved precision without excessive deployment costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a network-wide clock synchronization method based on IEEE 1588 protocol is used with a single time source at gateway or BBU-center, then the system structure is simple and deployment cost is low, but synchronization precision deteriorates due to long clock paths and error accumulation

Engineering Contradiction:
Improvesynchronization precisionVSAvoidsystem structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the network into multiple clock domains, each with its own master clock, rather than using a single centralized time source. This segmentation reduces the clock path length within each domain and prevents error accumulation over long distances, thereby improving synchronization precision while maintaining reasonable system complexity through modular organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the clock synchronization system by organizing multiple master clocks across different clock domains in a tree-like structure. This dimensional organization allows the system to achieve high precision locally within each domain while maintaining overall network synchronization, resolving the contradiction between precision and complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If the clock path length is increased to cover the entire network, then more nodes can be synchronized, but synchronization precision deteriorates due to error accumulation

Engineering Contradiction:
Improvesynchronization precisionVSAvoidclock path length
Core Design Contradiction:
Measurement precisionVSLength of stationary object

Solution Approach 1:

By segmenting the network into multiple clock domains with limited scopes, the patent ensures that each domain has a manageable clock path length. This prevents error accumulation that would occur in a single long clock path spanning the entire network, while still achieving network-wide synchronization through the hierarchical organization of multiple domains.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If higher precision synchronization is implemented across the entire network, then synchronization precision is improved, but deployment cost increases excessively

Engineering Contradiction:
Improvesynchronization precisionVSAvoiddeployment cost
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent implements high-precision synchronization locally within each clock domain using domain-specific master clocks, rather than deploying expensive high-precision infrastructure across the entire network. This local quality approach achieves the required precision for each domain's specific needs while significantly reducing overall deployment costs through selective, targeted implementation.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3104556B1Clock synchronization method and device, and communication system
Publication Date: 2023.07.05 HUAWEI TECH CO LTD
  • EP3104556B1 patent drawingFigure 1~2
  • EP3104556B1 patent drawingFigure 3
  • EP3104556B1 patent drawingFigure 4

AI summary

Embodiments of the present invention provide a clock synchronization method and device and a communications system. The method includes: determining, by a first node device in a network, a first master clock according to a first clock data set of the first node device and a first clock data set of another node device in the network, and synchronizing to the first master clock, where the first clock data set includes a first clock domain selection parameter of a node device; and determining, by the first node device, a second master clock according to a second clock data set of the first node device and a second clock data set of another node device that belongs to a same first node clock domain as the first node device does, and synchronizing to the second master clock, where the second clock data set includes a second clock domain selection parameter of a node device, and the node clock domain is a second clock domain. In the embodiments of the present invention, clock synchronization precision of a radio access network can be further improved.