Clock Domain Synchronizer Using Frequency Phase Estimation
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Solution Overview
Problem
Traditional periodic synchronizers for clock domains face limitations such as significant area overhead and latency due to the use of asynchronous FIFOs and Gray-coded pointers, which complicate signal synchronization across clock domains.
Innovation Solution
The system calculates a frequency and phase estimate of a first clock domain using frequency and phase estimators, determining a safe time to sample signals from the first clock domain, thereby avoiding the need for asynchronous FIFOs and reducing latency by synchronizing signals using all-digital periodic synchronizers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous FIFOs are used for signal synchronization between clock domains, then signal synchronization reliability is improved, but area overhead increases significantly
Solution Approach 1:
The patent extracts and eliminates the asynchronous FIFO memory structure from the synchronization system. Instead of using FIFOs to buffer and synchronize signals between clock domains, the invention directly samples the input signal at the output clock edge, removing the need for large-area storage structures while maintaining synchronization functionality through frequency and phase estimation.
Solution Approach 2:
The patent replaces the mechanical/memory-based FIFO structure with a computational approach using frequency and phase estimators. These estimators calculate the appropriate sampling time based on clock characteristics, substituting physical storage mechanisms with mathematical modeling and timing prediction, thereby reducing area overhead while preserving synchronization reliability.
2Measurement precision
If Gray-coded pointers are used in FIFO synchronizers, then signal synchronization accuracy is improved, but latency increases due to multiple flip-flop stages
Solution Approach 1:
The patent removes the Gray-coded pointer synchronization mechanism entirely. Instead of using multi-stage flip-flop chains to synchronize pointers, the invention directly determines sampling timing by estimating frequency and phase of the input clock, eliminating the intermediate pointer structures and their associated latency.
Solution Approach 2:
The patent performs preliminary frequency and phase estimation of the input clock before the actual sampling operation. By calculating the expected sampling time in advance based on clock characteristics, the system avoids the need for multi-stage synchronization of pointers, achieving both accuracy and low latency through pre-computed timing information.
3Reliability
If traditional periodic synchronizers are used, then signal synchronization is achieved, but device complexity increases due to FIFO and pointer structures
Solution Approach 1:
The patent extracts and removes the complex FIFO memory and Gray-coded pointer structures from the synchronizer. The invention replaces these complex components with simple frequency and phase estimators that calculate sampling timing, dramatically reducing device complexity while maintaining synchronization reliability through direct sampling at the estimated optimal time.
Solution Approach 2:
The patent substitutes mechanical/memory-based synchronization structures (FIFOs and pointers) with a computational timing prediction system. Frequency and phase estimators use mathematical models to predict the optimal sampling moment, replacing complex physical structures with simpler computational logic that achieves the same synchronization function with reduced complexity.
Data Source
AI summary
A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.