Simultaneous Clock Domain Testing via Controlled Pulse Sequences
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Solution Overview
Problem
Testing multiple clock domains in microprocessor designs separately is time-consuming and inefficient due to the need for sequential testing and reconfiguration of clock frequencies, which increases manufacturing costs and testing time.
Innovation Solution
Implementing a method and apparatus for simultaneous transition testing of different clock domains using test control circuits associated with each domain, allowing them to operate at their target frequencies with a controlled order of clock pulses, enabling coordinated testing and reducing overall testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential testing of each clock domain is performed, then testing accuracy is maintained, but testing time increases
Solution Approach 1:
The microelectronic circuit is divided into multiple clock domains, each with its own test control circuit. This segmentation allows independent control and simultaneous testing of each domain while maintaining the accuracy requirements for each individual domain through dedicated test control circuits.
Solution Approach 2:
Multiple clock domains are combined into a single integrated circuit that can be tested simultaneously. The test control circuits are synchronized to operate together, enabling parallel testing of multiple domains while maintaining the measurement precision required for each domain through coordinated control.
2Reliability
If separate testing of each clock domain is conducted, then testing thoroughness is improved, but manufacturing cost increases
Solution Approach 1:
The test control circuits are designed with multi-functionality, capable of controlling multiple clock domains simultaneously. This universal design allows a single testing apparatus to perform comprehensive testing of all clock domains, maintaining thoroughness while reducing manufacturing costs by eliminating the need for separate dedicated testing equipment for each domain.
Solution Approach 2:
The testing system dynamically changes operating parameters such as clock frequencies and test patterns to accommodate different clock domains. This parameter flexibility allows thorough testing of each domain's specific requirements while using a single versatile testing apparatus, thereby reducing manufacturing costs.
3Measurement precision
If reconfiguration of clock frequencies is performed for each domain, then testing accuracy is maintained, but testing complexity increases
Solution Approach 1:
Clock frequencies and test parameters are pre-configured for each clock domain before testing begins. The test control circuits are programmed with domain-specific parameters in advance, allowing accurate testing of each domain without requiring complex real-time reconfiguration during the testing process.
Solution Approach 2:
The testing system incorporates feedback mechanisms that automatically adjust test parameters based on the clock domain being tested. This feedback control maintains testing accuracy for each domain while reducing the complexity of manual reconfiguration by using automated parameter adjustment based on domain identification.
Data Source
AI summary
Implementations of the present disclosure involve an apparatus and/or method for conducting simultaneous transition testing of different clock domains of a microprocessor design at different frequencies through a controlled order of clock pulses in each domain. In general, a microelectronic design utilizes test control circuitry associated with each clock domain of the design to conduct simultaneous transition testing of the clock domains. The testing control circuitry associated with each clock domain of the microelectronic design further allows for the testing device to delay testing within a particular clock domain. By delaying the testing within a particular clock domain, the testing of the various clock domains can be synchronized. Through these testing procedures, the amount of time required to perform the ATPG testing of a microelectronic design may be greatly reduced.