Asynchronous Clock Domain Time Synchronization via Phase-Adjusted Counter Sampling
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Solution Overview
Problem
The transfer of accurate time information between different clock domains is hindered by errors introduced due to differences in clock periods and phase differences between master and slave clocks, leading to inaccuracies in time synchronization across network nodes.
Innovation Solution
A method where a first counter is sampled at a predetermined phase relationship with a second asynchronous counter, allowing for error correction by adjusting the increment values of the second counter to synchronize it with the first counter, thereby reducing errors to within the bounds of the fastest clock's period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a master counter is sampled using a slave clock with a different period, then the time transfer can be performed between clock domains, but dynamic errors occur due to period differences
Solution Approach 1:
The patent implements a feedback mechanism where the slave counter is periodically corrected based on the difference between the master counter value (sampled at slave clock edges) and the slave counter value. This closed-loop correction eliminates accumulation of period differences and maintains long-term synchronization accuracy.
Solution Approach 2:
The patent performs preliminary calibration by measuring the actual period of the slave clock relative to the master clock period. This measured ratio is then used to pre-calculate correction values that are applied to the slave counter, preventing error accumulation before it occurs.
2Adaptability or versatility
If counter values are transferred between asynchronous clock domains, then clock domain crossing is enabled, but phase differences cause additional timing errors
Solution Approach 1:
The patent uses periodic sampling of the master counter at slave clock edges, combined with periodic correction cycles. This rhythmic approach allows the system to tolerate phase differences by repeatedly realigning the counters at predictable intervals, converting a continuous error problem into a manageable periodic correction problem.
3Ease of operation
If the slave counter uses fixed increment values, then the counter operation is simple, but synchronization drift occurs over time
Solution Approach 1:
The patent transitions from static fixed increment values to dynamic adjustable increment values. The slave counter increment is periodically adjusted based on measured drift and the calculated correction values, allowing the system to adapt to frequency variations while maintaining synchronization. This dynamic adjustment prevents long-term drift without requiring continuous complex control.
Data Source
AI summary
In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.