Clock Domain Resynchronization Using Stored Timing Offsets
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Solution Overview
Problem
Integrated circuits with multiple clock domains face challenges in maintaining reliable communications and timing alignment when transitioning between power states, as existing link training methods require multiple circuits to re-establish timing relationships, consuming power and resources.
Innovation Solution
The implementation of a system where core and I/O circuits in different clock domains store timing offset values during initial link training, allowing for direct re-establishment of timing relationships when power is restored without performing a full link training operation, using components like multiplexers, FIFO circuits, and comparators to adjust latency and synchronize clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full link training is performed to re-establish timing relationships after power state transition, then reliable communication between clock domains is ensured, but time consumption and resource usage increase significantly
Solution Approach 1:
The patent stores timing offset values in memory during initial link training before power state transitions occur. When a power state transition happens, the stored timing offset values are retrieved and applied directly, eliminating the need to perform full link training again. This preliminary action of storing critical timing information enables rapid re-synchronization without time-consuming re-training sequences.
Solution Approach 2:
The patent creates a copy of the timing offset values from the original link training process and stores them in memory. Instead of re-performing the entire link training operation, the system uses these copied timing offset values to quickly re-establish timing relationships between clock domains after power state transitions, significantly reducing the time required while maintaining communication reliability.
2Reliability
If full link training is performed to re-establish timing relationships after power state transition, then timing alignment between clock domains is restored, but resource consumption increases
Solution Approach 1:
The timing offset values are predetermined and stored in memory during initial link training. When power state transitions occur, the system simply retrieves and applies these pre-calculated values rather than performing resource-intensive link training operations. This eliminates unnecessary computation and resource usage while ensuring timing alignment is properly restored.
Solution Approach 2:
The patent copies the timing offset values from the original link training process and stores them for later reuse. This copying approach allows the system to avoid repeating resource-consuming link training operations, instead using the stored copies of timing parameters to efficiently re-establish timing alignment with minimal resource consumption.
3Loss of time
If timing offset values are stored and used for quick re-synchronization, then time and resource consumption are reduced, but system complexity increases
Solution Approach 1:
The patent introduces memory as an intermediary component to store timing offset values. This memory element acts as a mediator between the link training process and the operational phases, allowing timing information to be preserved and quickly retrieved. The added complexity is localized to the memory storage and retrieval mechanism, which is a standard component in digital systems, rather than requiring complex control logic or additional processing circuits.
Data Source
AI summary
Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.