Clock Domain Data Transfer Control Module for Frequency Changes
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Solution Overview
Problem
Conventional methods for data transfer between clock domains in processors often result in meta-stability errors, which can be exacerbated by changes in clock frequency or power modes, leading to latency and additional circuitry requirements, and may introduce errors when using FIFOs.
Innovation Solution
A processor employs a control module that monitors clock edges to maintain a minimum setup time for data transfer across clock domains, ensuring accurate storage and retrieval by managing pointers to a FIFO, thereby preventing errors during frequency changes without requiring a reset or additional power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FIFO buffer is used to transfer data across clock domains, then data transfer reliability is improved, but errors occur when clock frequency changes due to voltage droop or power mode changes
Solution Approach 1:
The patent implements dynamic adjustment of the FIFO buffer's read/write pointers based on real-time clock frequency monitoring. When frequency changes are detected, the system dynamically modifies the timing of pointer updates to maintain proper setup and hold times, allowing the FIFO to adapt to frequency variations without errors
Solution Approach 2:
The system incorporates feedback mechanisms that continuously monitor clock frequency and voltage levels, and use this information to adjust FIFO operation parameters. This feedback loop enables the system to detect frequency changes and compensate by modifying buffer access timing, preventing data transfer errors during dynamic frequency transitions
2Reliability
If meta-stability circuits are added to prevent meta-stability errors, then data transfer accuracy is improved, but latency increases and additional circuitry is required
Solution Approach 1:
The patent extracts the critical timing control logic from traditional meta-stability circuits and implements it as a separate frequency monitoring and control mechanism. This allows the system to achieve data transfer accuracy through intelligent pointer management rather than relying on multiple synchronizer stages, reducing latency while maintaining reliability
Solution Approach 2:
The system introduces an intermediary frequency monitoring module that mediates between the clock domains and the FIFO buffer. This intermediary monitors frequency changes and adjusts buffer operation accordingly, eliminating the need for complex meta-stability circuits while preventing timing errors through proactive frequency management
3Device complexity
If conventional FIFOs are used for data transfer, then device complexity is reduced, but errors occur during frequency changes requiring reset or additional power consumption
Solution Approach 1:
The patent implements self-service functionality where the FIFO system automatically detects frequency changes and adjusts its own operation parameters without external intervention. The built-in frequency monitoring enables the FIFO to self-correct timing issues during frequency transitions, maintaining reliability without requiring system resets or additional power consumption
Data Source
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AI summary
A processor (100) maintains a minimum setup time for data being transferred between clock domains (102, 103), including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules (122, 124) that monitor clock edges in each of the clock domains to ensure that data is not accessed by the receiving clock domain from a storage location until a minimum number of phases have elapsed in the transferring clock domain after the data has been written to the storage location. Further, the control module maintains the minimum setup time in response to a change in clock frequency at one or both of the clock domains.