Clock Domain Data Transfer Using Handshake Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for data transfer between processors in different clock domains are either expensive due to the need for multiple registers or require generating a mutual clock rate, which can be complex and resource-intensive.
Innovation Solution
A method involving reading data into a memory in one clock domain, generating a transfer start signal, and then transferring it to another memory in a different clock domain, using a handshake protocol with transfer start and end signals to synchronize data transfer across clock domains, allowing for efficient data exchange without the need for multiple registers or complex clock rate synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a central register with shadow registers is used for data transfer between processors in different clock domains, then data exchange is enabled, but the space requirement increases significantly and cost increases
Solution Approach 1:
The patent extracts the data transfer function from the traditional register-based approach and implements it using memory structures with control signals. Instead of using multiple shadow registers, the invention uses a single memory location with locking mechanisms and control signals (READY, ACK) to enable data transfer between clock domains, significantly reducing the quantity of storage elements required.
Solution Approach 2:
The memory structure in the patent serves multiple functions: it acts as both the data transfer medium and the synchronization mechanism. The same memory location is used for data storage, while associated control signals (READY, ACK, locking) provide synchronization between different clock domains, eliminating the need for separate shadow registers.
2Reliability
If a mutual clock rate is generated for data exchange between processors, then synchronized communication is achieved, but the system complexity and resource requirements increase
Solution Approach 1:
The patent introduces control signals (READY, ACK) as intermediaries between the two clock domains. Instead of synchronizing the clock rates themselves, the invention uses these control signals to mediate the data transfer process, allowing processors operating at different clock rates to exchange data reliably without requiring complex clock synchronization circuitry.
Solution Approach 2:
The patent implements dynamic control of the data transfer process through control signals that adapt to the timing requirements of each clock domain. The READY signal indicates when data is ready to be transferred, and the ACK signal confirms successful reception, allowing the system to dynamically coordinate transfers without fixed clock synchronization.
3Adaptability or versatility
If multiple registers are provided for data transfer between clock domains, then data exchange is possible, but the manufacturing cost and space requirements increase
Solution Approach 1:
The patent merges the data storage function and the synchronization function into a single integrated mechanism. Instead of providing separate registers for data storage and separate control logic for synchronization, the invention combines these functions using memory structures with associated control signals (READY, ACK, locking), reducing the total number of components and manufacturing cost.
Data Source
AI summary
The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK1) and at least one additional clock domain having a second clock rate (CLK2), comprising the following for the transfer of data from the first to the second clock domain (CLK1, CLK2):reading in of a data item in accordance with the first clock rate (CLK1) into a first memory (11), and locking of the first memory after saving the data item,signalizing a transfer start after saving the data item in the first memory (11) by means of a transfer start signal (TS),reading out the data item from the first memory, and reading in the data item into a second memory, each according to the second clock signal (CLK2),processing the transfer start signal (TS) according to the second clock signal (CLK2) for generating a transfer end signal (TD),processing the transfer end signal (TD) according to the first clock signal (CLK1) for generating a release signal (TD′) and releasing the first memory as a function of the release signal (TD′).