Asynchronous Clock Domain Synchronization Using Triggered Timer Counts
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Solution Overview
Problem
Existing clock synchronization methods in integrated circuits face challenges in efficiently synchronizing asynchronous clock domains, leading to synchronization failures, increased clock jitter, and delays due to multiple communication stages and non-homologous clock sources, which affect timing accuracy and resource utilization.
Innovation Solution
A method involving a trigger signal to record current count values of timers in different clock domains, allowing for clock compensation by comparing and synchronizing these values to synchronize the clock domains, reducing the number of communication stages and improving accuracy by eliminating synchronization failures and minimizing the impact of clock jitter and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple communication stages are used for clock synchronization between different clock domains, then the synchronization can be achieved, but the synchronization time increases and productivity decreases
Solution Approach 1:
The patent segments the clock synchronization process into two independent one-way timestamp exchanges instead of multiple iterative communication stages. The first module sends its timestamp, the second module sends its timestamp, and both timestamps are used together for compensation calculation, eliminating the need for multiple back-and-forth communication stages while maintaining synchronization reliability.
Solution Approach 2:
The patent performs preliminary timestamp recording at the moment each module generates its clock timestamp, before any communication occurs. This preliminary action captures the exact clock state without requiring subsequent communication stages to query or verify timing information, thereby reducing synchronization time while ensuring accuracy.
2Reliability
If traditional clock synchronization methods are used with non-homologous clock sources, then clock domains can be synchronized, but clock jitter and delay increase affecting timing accuracy
Solution Approach 1:
The patent implements a feedback mechanism where both modules record their respective timestamps and exchange them, then use the received timestamp along with the local timestamp to calculate compensation values. This feedback loop allows each module to adjust its timing based on the actual time difference observed, thereby compensating for clock jitter and delay effects from non-homologous clock sources and improving synchronization accuracy.
Solution Approach 2:
The patent changes the timing parameter by recording timestamps at the exact moment clock edges occur rather than using fixed periodic sampling. This parameter change allows the system to capture actual clock behavior including jitter and delay, and the compensation calculation adjusts for these variations, thereby maintaining high synchronization accuracy even with non-homologous clock sources.
3Reliability
If multiple communication stages are implemented for clock synchronization, then synchronization can be achieved, but the number of communication interfaces increases device complexity
Solution Approach 1:
The patent merges the clock synchronization function with existing data communication interfaces. The same interface used for normal data exchange between modules is also used for transmitting timestamp information. By combining these functions, the patent achieves reliable clock synchronization without adding dedicated synchronization interfaces, thereby reducing device complexity while maintaining synchronization reliability.
Solution Approach 2:
The patent makes the communication interface universal by enabling it to serve both data communication and clock synchronization purposes. The interface transmits both regular data and timestamp information, and the receiving module processes both types of information appropriately. This multi-functionality eliminates the need for separate synchronization interfaces, reducing overall device complexity while ensuring reliable synchronization.
4Measurement precision
If frequent clock synchronization is performed, then timing accuracy is maintained, but resource utilization decreases due to increased communication overhead
Solution Approach 1:
The patent implements periodic clock synchronization where modules exchange timestamps at predetermined intervals rather than continuously or on every event. This periodic action maintains timing accuracy by regularly updating synchronization information while avoiding excessive communication overhead. The interval is optimized to balance timing accuracy requirements with resource utilization, preventing unnecessary communication when clock drift is minimal.
Data Source
AI summary
A clock synchronization method and apparatus, an electronic device and a storage medium are provided. The clock synchronization method includes: sending a trigger signal to a second processing module and recording a current count value of the first timer upon sending the trigger signal as a first count value; and reading a second count value from the second processing module, the second count value is a current count value of a second timer of the second processing module upon the second processing module receiving the trigger signal, and a count value of the second timer is used as a timing reference of the second processing module and sequentially increasing; the first count value and the second count value are used for a clock compensation to synchronize a first clock domain where the first processing module is located with a second clock domain where the second processing module is located.