Clock Frequency Doubler Using Digital Programmable Delay
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Solution Overview
Problem
Conventional clock frequency doubling circuits require large chip areas and high power consumption, and struggle to maintain a 50% duty cycle, which is crucial for accurate signal processing and audio systems to prevent distortion.
Innovation Solution
The proposed solution involves a clock frequency doubler circuit that uses digital programmable delay circuits and a Successive Approximation Register (SAR) Time-to-Digital Converter (TDC) to generate clock pulses at both rising and falling edges, ensuring a 50% duty cycle by adjusting delay times with high accuracy, thereby reducing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PLL or FLL circuits are used for clock frequency doubling, then the clock frequency can be doubled, but the chip area becomes large and power consumption increases
Solution Approach 1:
The patent extracts the essential function of frequency doubling from complex PLL/FLL circuits by using only the core components: a delay element and a pulse generator. This extraction removes unnecessary circuitry, achieving frequency doubling with minimal chip area while maintaining the core functionality.
Solution Approach 2:
The patent uses a simple delay element that can be easily copied and integrated into the frequency doubler circuit. The delay element is designed to be compact and can be replicated, allowing the circuit to achieve frequency multiplication without requiring large areas for complex control logic.
2Speed
If conventional PLL or FLL circuits are used for clock frequency doubling, then the clock frequency can be doubled, but power consumption increases
Solution Approach 1:
The patent extracts only the essential energy-consuming components needed for frequency doubling, eliminating the high-power control logic and feedback mechanisms of PLL/FLL circuits. The resulting circuit uses minimal power while achieving the same frequency multiplication function.
Solution Approach 2:
The patent employs simple, low-power delay elements and pulse generators that consume minimal energy. These components are designed to be lightweight in terms of power consumption, providing the necessary frequency doubling function with significantly reduced power requirements compared to conventional circuits.
3Speed
If pulses are generated on both positive and negative edges without duty cycle control, then frequency doubling is achieved, but the duty cycle cannot be maintained at 50%
Solution Approach 1:
The patent incorporates feedback mechanisms that monitor the duty cycle of the generated clock signal and adjust the delay element accordingly. This feedback ensures that the duty cycle remains at 50% even as the input frequency varies, maintaining precision in the frequency doubling process.
Solution Approach 2:
The patent dynamically adjusts the delay parameter of the delay element based on the input frequency to maintain a 50% duty cycle. By changing the delay parameter in response to frequency variations, the circuit achieves both frequency doubling and duty cycle precision simultaneously.
Data Source
AI summary
In a clock frequency doubler, an input clock feeds into a digital programmable delay circuit, and an inverted input clock feeds into another digital programmable delay. The outputs of these digital programmable delay circuits are combined with the input clock and inverse clock through AND gates in order to generate clock pulses at both the rising and falling edge of the clock. These signals are combined using an OR gate to provide an output clock signal with a frequency that is double the frequency of the input clock signal. The values of the control bits for the digital programmable delay circuit are determined in a time-to-digital conversion (TDC) circuit that includes a Successive Approximation Register (SAR). For every cycle of the clock, the SAR circuit successively sets the programmable delay control bits and compares the delay circuit output with the input clock to determine the value of the control bits.