Clock Doubler Circuit for 50% Duty Cycle and Fast Start-Up
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing frequency doublers face challenges in achieving a 50% duty cycle with fast start-up time, particularly in applications like analog to digital converters where a clock frequency twice that of the master clock is required, as phase locked loops are ineffective in providing quick stabilization and other methods like variable delays with XOR gates take time to stabilize.
Innovation Solution
A clock doubler circuit comprising a low pass filter, frequency doubling circuit, and clock shaping circuit that converts a square wave clock into filtered true and complementary clocks with slower transition times, utilizing transistors and capacitors to generate a doubled clock with comparable transition times and a 50% duty cycle, and includes a tunable configuration to adjust the switch point for precise duty cycle achievement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If phase locked loops are used to achieve 50% duty cycle, then duty cycle precision is improved, but start-up time increases
Solution Approach 1:
The frequency doubler is divided into two independent functional blocks: a duty cycle correction block that ensures 50% duty cycle and a frequency doubling block that generates the doubled frequency. This segmentation allows each block to be optimized independently, enabling fast start-up while maintaining precise duty cycle control without requiring phase locked loops.
2Productivity
If variable delays with XOR gates are used to double frequency, then frequency doubling is achieved, but duty cycle stabilization time increases
Solution Approach 1:
The duty cycle correction block performs preliminary correction of the duty cycle before the signal enters the frequency doubling block. By pre-correcting the duty cycle to 50%, the subsequent frequency doubling operation can proceed immediately without requiring stabilization time, thus achieving fast frequency doubling with stable duty cycle.
3Speed
If fast transition times are maintained in doubled clock, then speed is improved, but duty cycle precision becomes difficult to achieve
Solution Approach 1:
The duty cycle correction block selectively modifies only the transition regions of the clock signal to achieve 50% duty cycle, while preserving the fast transition characteristics in the main signal path. This local modification approach ensures that the overall signal maintains fast transition times while achieving precise duty cycle control at critical points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively doubles the frequency of the input clock while achieving a 50% duty cycle with fast transition times, addressing the limitations of existing methods by providing a stable and efficient frequency doubling circuit with precise control over the duty cycle.
Implementation Method 1
a low pass filter, frequency doubling circuit, and clock shaping circuit that converts a square wave clock into filtered true and complementary clocks with slower transition times
Implementation Method 2
utilizing transistors and capacitors to generate a doubled clock with comparable transition times and a 50% duty cycle
Data Source
AI summary
A clock doubler circuit includes a filtering circuit. The filtering circuit includes a first input to receive a first clock signal, a first output to provide a second clock signal, and a second output to provide a third clock signal. The third clock signal is a complementary signal to the second clock signal. The first clock signal, the second clock signal, and the third clock signal are at a first clock frequency. The second clock signal is a low pass filtered version of the first clock signal. The clock doubler circuit includes a frequency doubling circuit. The frequency doubling circuit includes a first input to receive the second clock signal and a second input to receive the third clock signal. The frequency doubling circuit includes an output node. The output node provides a fourth clock signal at a second clock frequency that is twice the first clock frequency.