Clock Doubler Duty Cycle Correction Circuit
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Solution Overview
Problem
Existing clock signal generation methods face challenges in achieving a 50% duty cycle due to device mismatches, especially at high frequencies, leading to power inefficiency and significant duty cycle distortion when attempting to operate oscillators at twice the desired frequency.
Innovation Solution
A clock doubler circuit with dual charge pumps and mismatch correction mechanisms, where each charge pump operates on alternate cycles to detect and correct current mismatches, ensuring a 50% duty cycle by adjusting currents to match, thereby generating a clock signal with improved timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an oscillator is run at twice the desired frequency and divided by two to generate a clock signal, then the duty cycle is improved, but power consumption increases and significant duty cycle distortion remains due to random device mismatches
Solution Approach 1:
The patent implements a feedback mechanism where the clock signal is fed back to the duty cycle correction circuit, which continuously monitors and adjusts the clock signal to maintain a 50% duty cycle. This closed-loop feedback system corrects duty cycle distortion without requiring the oscillator to run at twice the frequency, thereby reducing power consumption while maintaining duty cycle accuracy.
Solution Approach 2:
The patent changes the operating parameters by running the oscillator at the desired frequency rather than twice the frequency. The duty cycle correction circuit then adjusts the clock signal parameters (duty cycle) through controlled delay adjustment, eliminating the need for high-frequency operation and reducing power consumption while achieving the desired duty cycle accuracy.
2Manufacturing precision
If an oscillator is run at twice the desired frequency and divided by two to generate a clock signal, then the duty cycle is improved, but significant duty cycle distortion remains due to random device mismatches
Solution Approach 1:
The feedback mechanism continuously monitors the clock signal duty cycle and adjusts the delay element to maintain a 50% duty cycle. This real-time correction compensates for random device mismatches in the divide-by-2 circuit, significantly reducing duty cycle distortion and improving reliability compared to the conventional approach.
Solution Approach 2:
The duty cycle correction circuit performs preliminary adjustment on the clock signal before it is used by synchronous circuits. By pre-correcting the duty cycle distortion through delay adjustment, the system ensures that the clock signal has the desired 50% duty cycle, compensating for device mismatches before they affect circuit operation.
3Manufacturing precision
If device mismatches are minimized through careful design, then duty cycle accuracy is improved, but this becomes increasingly difficult at high frequencies with smaller clock periods
Solution Approach 1:
The feedback-based duty cycle correction circuit automatically compensates for device mismatches without requiring extremely precise manual design adjustments. The system continuously monitors and corrects duty cycle errors, making the design process simpler and more robust, especially at high frequencies where small mismatches would otherwise cause significant duty cycle distortion.
Solution Approach 2:
The duty cycle correction circuit is self-adjusting and automatically compensates for device mismatches without requiring external calibration or complex design procedures. The system serves itself by continuously monitoring its own performance and making real-time adjustments, reducing the burden on the design process while maintaining high duty cycle accuracy at high frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively corrects duty cycle mismatches, reducing power consumption and distortion, and achieves a clock signal with optimal timing margins, suitable for high-speed digital circuits.
Implementation Method 1
dual charge pumps and mismatch correction mechanisms, where each charge pump operates on alternate cycles to detect and correct current mismatches
Data Source
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AI summary
Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock.