Clock Frequency Doubler with Duty-Cycle Correction and T/4 Delay
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Solution Overview
Problem
Existing clock doubling systems face issues in efficiently doubling the frequency of an input clock signal while maintaining a 50% duty cycle, leading to unwanted spurious tones in the output spectrum, and they do not effectively manage power consumption.
Innovation Solution
A method and apparatus that utilize a duty cycle corrector and a T/4 delay generator to produce an output clock signal with a doubled frequency and a 50% duty cycle, employing a digital delay locked loop to estimate and correct the duty cycle, and XORing the corrected signal with a T/4 delayed version to generate the output, which also includes calibration processes to optimize delay settings and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a prior art clock doubling system is used, then the frequency of the input clock signal is doubled, but unwanted spurious tones appear in the output spectrum and the duty cycle cannot be maintained at 50%
Solution Approach 1:
The duty cycle estimator and corrector perform preliminary adjustment of the clock signal duty cycle before the frequency doubling operation. By pre-correcting the duty cycle to exactly 50%, the subsequent XOR-based frequency doubling produces a clean output spectrum without spurious tones, as the preliminary action eliminates the source of distortion.
Solution Approach 2:
A duty cycle corrector circuit is introduced as an intermediary component between the input clock signal and the frequency doubling stage. This intermediary actively adjusts the duty cycle of the input signal to precisely 50% before it undergoes frequency doubling, thereby preventing the generation of spurious tones in the final output.
2Manufacturing precision
If duty cycle estimation and correction circuits are added, then the duty cycle accuracy is improved, but the device complexity increases
Solution Approach 1:
The duty cycle estimation and correction functions are merged into a single integrated circuit block that processes the clock signal in one unified operation. By combining these functions rather than implementing them as separate stages, the circuit achieves high duty cycle accuracy while minimizing the increase in overall device complexity.
Solution Approach 2:
The duty cycle corrector circuit is designed to perform multiple functions simultaneously: it estimates the current duty cycle, calculates the required correction, and applies the adjustment all within a single circuit architecture. This multi-functionality reduces the need for additional separate components, thereby limiting the growth of device complexity.
3Use of energy by moving object
If calibration processes are implemented, then power consumption is reduced, but the ease of operation decreases
Solution Approach 1:
The calibration process is designed to be self-executing, where the circuit automatically performs duty cycle estimation and correction without requiring manual intervention. The system self-adjusts its parameters to optimize power consumption while maintaining accurate duty cycle, thereby reducing the burden on the operator despite the added calibration functionality.
Data Source
AI summary
A clock doubler circuit doubles the frequency of an input clock signal. The input clock signal is supplied to a duty cycle corrector (DCC) circuit, which generates a DCC output signal having a duty cycle corrected to fifty percent and has a frequency that equals the input frequency. A T/4 delay circuit receives the input clock signal and generates a T/4 delay output signal that has a delay of T/4 from the DCC output signal and has the same frequency as the input clock signal. T/4 is one quarter of a period of the input clock signal. An XOR gate combines the DCC output signal and the T/4 delay output signal to generate an output clock signal that is twice the frequency of the input clock signal. A duty cycle estimator generates correction factors used to generate the T/4 delay output signal and the DCC output signal.