Clock Frequency Doubler With Duty Cycle Feedback Correction
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Solution Overview
Problem
Existing clock multiplier systems fail to produce a high-frequency clock signal with uniformly spaced edges due to varying duty cycles, leading to unstable frequency multiplication when the duty cycle of the input clock signal is not 50%, resulting in oscillating period lengths and unsuitable output waveforms.
Innovation Solution
A clock multiplier circuit incorporating a clock generator, delay element, logic gate, and duty cycle correction circuit, which uses a timing loop and charge pump to adjust the duty cycle of the input clock signal based on the frequency-multiplied signal, ensuring uniform edge spacing by correcting duty cycle deviations from 50%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a frequency doubler circuit combines clock signal with delayed clock signal using XOR logic, then the frequency of the output clock signal is doubled, but the duty cycle of the clock signal affects the resulting waveform causing non-uniformly spaced edges
Solution Approach 1:
The patent implements a feedback mechanism where the output clock signal is fed back through a delay element and phase detector to generate control signals that adjust the duty cycle of the input clock signal. This closed-loop feedback system continuously monitors and corrects the duty cycle to maintain 50%, ensuring uniformly spaced edges in the frequency-multiplied output signal.
Solution Approach 2:
The patent dynamically changes the duty cycle parameter of the input clock signal from its original value to a corrected value of 50%. By adjusting this critical parameter through the duty cycle correction circuit, the system ensures that the XOR logic gate produces uniformly spaced edges in the output signal while maintaining the desired frequency multiplication.
2Productivity
If the duty cycle of the input clock signal is not 50%, then the frequency multiplication operation can be performed, but the period of the output clock signal oscillates between two values
Solution Approach 1:
The feedback loop continuously monitors the phase relationship between the output clock signal and its delayed version, generating control signals that adjust the input clock duty cycle. This real-time feedback stabilization ensures the period remains constant by preventing oscillations that would occur with non-50% duty cycles.
Solution Approach 2:
The duty cycle correction circuit performs preliminary adjustment of the input clock signal duty cycle to exactly 50% before the frequency multiplication operation. By pre-correcting the duty cycle parameter, the system prevents period oscillations from occurring in the first place, ensuring stable output from the XOR logic gate.
3Manufacturing precision
If a duty cycle correction circuit is added to correct the duty cycle to 50%, then uniformly spaced edges are achieved, but the device complexity increases
Solution Approach 1:
The patent employs a phase-locked loop (PLL) circuit that performs multiple functions: frequency multiplication, phase detection, and duty cycle correction. By utilizing the existing PLL infrastructure for its primary frequency synthesis function, the system achieves duty cycle correction without adding completely separate correction circuitry, thereby reducing overall complexity.
Solution Approach 2:
The duty cycle correction functionality is merged with the frequency multiplication operation by using the same feedback loop and phase detector that are already present in the frequency synthesis system. The correction circuit reuses existing components (delay element, phase detector, charge pump) to simultaneously achieve both frequency multiplication and duty cycle stabilization.
Data Source
AI summary
A clock multiplier circuit includes a clock generator, a delay element, a logic gate, and a duty cycle correction circuit. The clock generator generates a clock signal. The delay element generates a delayed clock signal in response to the clock signal. The logic gate generates a frequency-multiplied clock signal in response to the clock signal and the delayed clock signal. The duty cycle correction circuit generates an adjustment signal based at least in part on the frequency-multiplied clock signal. The clock generator adjusts a duty cycle of the clock signal in response to the adjustment signal.