Clock Drift Monitor Using XOR Phase Difference Detection
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Solution Overview
Problem
In avionics systems, independent clock sources must remain synchronized to ensure system redundancy, but existing methods lack effective monitoring for clock drift between these sources, which can lead to frequency discrepancies.
Innovation Solution
A circuit and method using an XOR gate to generate a switching output based on the phase difference between two clock signals, with edge detectors and a configurable threshold to detect clock drift, providing an indication of fault conditions without requiring frequency counters or phase-locked loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequency counters or phase-locked loops are used to monitor clock drift, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential function needed for clock drift detection by using a simple XOR gate to generate a switching output based on phase difference, eliminating the need for complex frequency counters or phase-locked loops while maintaining adequate measurement precision for monitoring purposes
Solution Approach 2:
The patent replaces expensive, complex measurement instruments (frequency counters, phase-locked loops) with a simple, inexpensive digital logic circuit using basic gates (XOR, AND, NOT) that can be easily implemented in integrated form, reducing both complexity and cost
2Measurement precision
If high-frequency measurement techniques are used, then measurement precision is improved, but ease of manufacture worsens
Solution Approach 1:
The patent substitutes complex high-frequency measurement techniques with a simple digital logic-based switching output approach, where the XOR gate naturally produces a signal whose frequency content reflects the clock drift, eliminating the need for complex high-frequency measurement hardware and simplifying board layout
3Reliability
If independent clock sources are used for system redundancy, then reliability is improved, but clock synchronization becomes more difficult to maintain
Solution Approach 1:
The patent implements a self-monitoring system where the XOR gate automatically generates a switching output that reflects the phase difference between independent clock sources, and the subsequent logic circuitry automatically detects when this phase difference exceeds acceptable thresholds, providing autonomous synchronization monitoring without external intervention
Solution Approach 2:
The patent creates a feedback mechanism by continuously monitoring the switching output from the XOR gate and using the detected phase difference information to generate fault indications when clock drift exceeds thresholds, enabling real-time feedback on synchronization status to maintain reliability
Data Source
AI summary
Provided are embodiments for monitoring clock drift. Embodiments may include an XOR gate that is configured to receive a first clock signal from a first clock source and a second clock signal from a second clock source, wherein the XOR logic gate is further configured to generate a switching output based on an XOR operation of the first clock signal and the second clock signal, and a rising edge detector and a falling edge detector that are configured to detect a rising edge and a falling edge of the switching output. Embodiments may also include an AND gate that is configured to threshold compare the rising edge to a configurable threshold to determine if a fault condition exists indicating clock drift between the first clock signal and the second clock signal and provide an indication of the fault condition based at least in part on the comparison.