Clock Driver Body Biasing for Impedance-Matched Amplitude Control

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Solution Overview

Problem

Clock driver circuits face challenges in maintaining output impedance matching for different output amplitude levels, leading to degradation in return loss when switching between high and low amplitude states.

Innovation Solution

The proposed solution involves an output impedance adjusting circuit with a diode-connected transistor, a bypass transistor, a resistor, and a pull-down transistor, which applies different body voltages to the transistor based on the supply voltage state, reducing the impedance difference between states and maintaining high return loss across varying amplitudes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the supply voltage is reduced to lower the output amplitude, then the power consumption is reduced, but the output impedance changes causing return loss degradation

Engineering Contradiction:
Improvepower consumptionVSAvoidreturn loss
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies body biasing to dynamically adjust the body voltage of the output transistor based on the supply voltage state. When the supply voltage is reduced to lower power consumption, the body voltage is simultaneously adjusted to compensate for the impedance change, maintaining consistent output impedance and return loss across different amplitude levels

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the body voltage is controlled based on the supply voltage state. The control circuit monitors the supply voltage and adjusts the body voltage accordingly to maintain optimal output impedance matching, ensuring return loss remains above 10 dB across different operating states

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If the output amplitude is varied to meet different application requirements, then the adaptability is improved, but the output impedance matching becomes difficult to maintain

Engineering Contradiction:
Improveoutput amplitude rangeVSAvoidoutput impedance matching
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent uses body biasing to dynamically change the body voltage parameter of the output transistor according to the supply voltage state. This allows the circuit to adapt to different output amplitude requirements while maintaining consistent output impedance characteristics and return loss performance across the full amplitude range

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates a universal clock driver circuit that can operate across multiple amplitude levels with consistent performance. By integrating body biasing control, the single circuit design achieves both amplitude variability for different applications and stable impedance matching, eliminating the need for separate circuits for different amplitude requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10826497B2Impedance matched clock driver with amplitude control
Publication Date: 2020.11.03 SAMSUNG ELECTRONICS CO LTD
  • US10826497B2 patent drawing
  • US10826497B2 patent drawing
  • US10826497B2 patent drawing

AI summary

A clock driver circuit. In some embodiments the clock driver circuit includes an output stage, a first voltage source, and an output impedance adjusting circuit. The output stage includes a first transistor connected to the first voltage source and to an output of the drive circuit. The drive circuit is configured to operate in one of, at least, a first state, and a second state. The output impedance adjusting circuit is configured to reduce a difference between an output impedance of the drive circuit in: the first state, in which the first transistor is turned on and the first voltage source is at a first supply voltage, and the second state, in which the first transistor is turned on and the first voltage source is at a second supply voltage different from the first supply voltage.