Clock Driver Chip-Enable Generation for DRAM Low-Power Mode
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Solution Overview
Problem
Semiconductor memories, particularly volatile memories like DRAM, face increased power consumption when in a clock interruption mode due to the lack of a separate pin for recognizing this mode, leading to inefficient power usage.
Innovation Solution
A clock driver generates a chip enable signal using a differential clock signal pair to transition between operational and interruption modes without an additional pin, utilizing a differential buffer and signal coupler to output a chip enable signal based on differential internal clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a clock buffer without a separate pin is used to recognize clock interruption mode, then device complexity is reduced, but power consumption increases due to inability to enter low power mode
Solution Approach 1:
The clock buffer is designed to perform multiple functions: it buffers the clock signal during normal operation and simultaneously detects clock interruption mode by monitoring the clock signal characteristics. This eliminates the need for a separate detection pin while enabling low power mode entry, thus resolving the contradiction between device complexity reduction and power consumption management.
Solution Approach 2:
The clock buffer uses its own buffered clock signal to detect the clock interruption mode without requiring external assistance or additional pins. By monitoring the clock signal itself, the system can autonomously determine when to enter low power mode, maintaining power efficiency while simplifying the device interface.
2Use of energy by moving object
If a separate pin is added for chip enable signal recognition, then power consumption control is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The clock buffer is designed to perform multiple functions: it buffers the clock signal during normal operation and simultaneously detects clock interruption mode by monitoring the clock signal characteristics. This eliminates the need for a separate detection pin while enabling low power mode entry, thus resolving the contradiction between device complexity reduction and power consumption management.
Solution Approach 2:
The clock interruption detection function is merged with the clock buffer functionality. The same circuit that buffers the clock signal also detects whether the clock has been interrupted, combining two functions into one component and eliminating the need for additional pins or circuits.
3Reliability
If differential clock signals are coupled to generate chip enable signal, then signal integrity is maintained, but circuit complexity increases
Solution Approach 1:
A differential buffer is introduced as an intermediary component that receives the differential clock signal and generates a differentiated signal that indicates clock interruption mode. This intermediary component maintains signal integrity by properly handling the differential signals while simplifying the overall detection logic, as the buffer outputs a clear indication signal that can be directly used for mode detection.
Data Source
AI summary
The present disclosure provides a clock driver, an operating method thereof, a memory device including the clock driver, and a memory system. A clock driver according to an embodiment includes a differential buffer configured to output a differential amplified clock signal pair based on a differential external clock signal pair, and a signal coupler configured to generate a differential internal clock signal pair based on the differential amplified clock signal pair, and output a chip enable signal to the memory chip based on the differential internal clock signal pair.