Internal Clock Driver Circuit for Non-Overlapping DLL Signals
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Solution Overview
Problem
Conventional DLL clock signal drivers face challenges in preventing overlap of rising and falling DLL clock signals at high frequencies, leading to distorted data and operational issues due to internal pulse generation and transistor performance limitations.
Innovation Solution
An internal clock signal driver circuit that delays rising and falling clock signals and generates non-overlapping rising and falling DLL clock signals using a delay block, pull-up and pull-down units, and latch units, without adjusting pulse widths, ensuring the rising edges are maintained.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL clock signal drivers are used to generate rising and falling DLL clock signals, then the signals can be generated with predetermined pulse widths, but the signals may overlap each other at high frequencies leading to distorted data
Solution Approach 1:
The patent implements dynamic control of the DLL clock signal generation by using latch units that respond to the actual timing relationships between rising and falling clock signals. The circuit dynamically adjusts the output signals based on real-time signal conditions, allowing reliable operation across varying frequencies without fixed pulse width limitations.
Solution Approach 2:
The patent employs feedback mechanisms where the latch units monitor the delayed rising and falling clock signals and use this information to control the generation of rising and falling DLL clock signals. This feedback ensures that the output signals do not overlap even when input signal characteristics change with frequency variations.
2Reliability
If internal pulses of prescribed width are generated to prevent overlap, then signal overlap is avoided at low frequencies, but the rising edges of DLL clock signals cannot be maintained at high frequencies
Solution Approach 1:
The patent uses delay units to advance-prepares delayed versions of the rising and falling clock signals before they are used by the latch units. This preliminary delay action allows the circuit to anticipate signal transitions and maintain proper timing relationships, ensuring rising edges are preserved even at high frequencies.
Solution Approach 2:
The latch units serve as intermediary elements between the delayed clock signals and the generated DLL clock signals. These latch units mediate the timing relationship by capturing the state of delayed signals at appropriate moments and using them to control the output, thereby maintaining rising edge integrity without requiring fixed pulse width adjustments.
3Adaptability or versatility
If delay units are used to adjust pulse widths of input clock signals, then pulse width control is achieved, but the complexity of the circuit increases
Solution Approach 1:
The patent designs the delay units and latch units to serve multiple functions simultaneously. The delay units not only provide timing adjustment but also work in conjunction with the latch units to enable dynamic pulse width control and rising edge maintenance. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby managing complexity while maintaining adaptability.
Data Source
AI summary
An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.